会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Digital data transmitting system for transmitting digital data a number
of times depending on an information content of the digital data
    • 数字数据发送系统,用于根据数字数据的信息内容多次发送数字数据
    • US4692816A
    • 1987-09-08
    • US626700
    • 1984-07-02
    • Hiroyuki SugiyamaNobuaki TakahashiTakeshi ShibamotoKazunori NishikawaMakoto Komura
    • Hiroyuki SugiyamaNobuaki TakahashiTakeshi ShibamotoKazunori NishikawaMakoto Komura
    • G11B20/18H04L1/08H04N9/806H04N5/85G11B20/12
    • H04L1/08G11B20/1803G11B20/1809H04N9/8066
    • A digital data transmitting system comprises a first circuit for transmitting digital data related to an information signal data in terms of sectors each having k words with respect to each channel, where k is a natural number. The transmission of the digital data is performed within a predetermined transmission time period once or a plurality of times according to a tolerance of data error rate for an information content of the digital data. The information signal data are among digital data related to a plurality of channels of information signals which are subjected to a digital modulation, and the plurality of channels of information signals are made up of a combination at least including the information signal data among three kinds of information signals. The three kinds of information signals are a non-compressed audio signal, a video signal, and the information signal data other than the non-compressed audio signal and the video signal. The system also comprises a second circuit for adding a code and a synchronizing signal to the digital data which are obtained from the first circuit, and for transmitting the digital data having the first code and the first synchronizing signal added thereto. The first code is at least indicative of a number of times the digital data are repeatedly transmitted within the predetermined transmission time period.
    • 数字数据发送系统包括:第一电路,用于根据关于每个信道具有k个字的扇区,发送与信息信号数据有关的数字数据,其中k是自然数。 数字数据的传输根据数字数据的信息内容的数据差错率的公差,在预定传输时间段内进行一次或多次。 信息信号数据是与进行数字调制的信道信号的多个信道有关的数字数据,多个信道信道的信道由至少包含3种信息信号的信息信号数据的组合构成 信息信号。 三种信息信号是非压缩音频信号,视频信号和除非压缩音频信号和视频信号之外的信息信号数据。 该系统还包括第二电路,用于将从第一电路获得的数字数据的码和同步信号相加,并且发送具有添加了第一码和第一同步信号的数字数据。 第一代码至少表示数字数据在预定传输时间段内重复发送的次数。
    • 4. 发明授权
    • Data producing device in a signal reproducing apparatus
    • 信号再现装置中的数据产生装置
    • US4667318A
    • 1987-05-19
    • US543402
    • 1983-10-19
    • Hiroyuki SugiyamaMakoto KomuraIsao MasudaKazunori NishikawaYoshiki Iwasaki
    • Hiroyuki SugiyamaMakoto KomuraIsao MasudaKazunori NishikawaYoshiki Iwasaki
    • G11B20/10G11B20/18G11B27/10G11B27/30G11B27/34H04N1/21H04N5/76G11B5/02
    • G11B20/10527G11B20/1809G11B27/105G11B27/3027G11B27/3036G11B27/34H04N1/2166G11B2220/20
    • A data producing device in a signal reproducing apparatus, comprises a shift register supplied with synchronizing signals and codes which are time-sequentially reproduced from a recording medium, synchronizing signal detectors supplied with the synchronizing signals from the shift register, data transfer circuits provided in parallel with respect to each other and in series with the synchronizing signal detectors, and a control circuit for controlling the data transfer circuits so that a data is selectively read out and produced from a desired data transfer circuit among the plurality of data transfer circuits. The reproduced synchronizing signals and codes are transferred to the shift register and are read out from the shift register in response to a clock pulse having a predetermined frequency. The number of the synchronizing signal detectors is equal to the number of kinds of the synchronizing signals, and the synchronizing signal detectors are provided in parallel with respect to each other. Each of the synchronizing signal detectors detect a specific synchronizing signal. A data in a predetermined code among the codes supplied to the data transfer circuits is transferred to the data transfer circuits, when a synchronizing signal for discriminating the predetermined code is detected in the synchronizing signal detectors and supplied to the data transfer circuits.
    • 信号再现装置中的数据产生装置包括:移位寄存器,其提供有从记录介质被时间顺序再现的同步信号和代码,提供有来自移位寄存器的同步信号的同步信号检测器,并行提供的数据传送电路 并且与同步信号检测器串联的控制电路,以及用于控制数据传送电路的控制电路,使得从多个数据传送电路中的期望的数据传送电路选择性地读出和产生数据。 再现的同步信号和代码被传送到移位寄存器,并且响应于具有预定频率的时钟脉冲从移位寄存器读出。 同步信号检测器的数量等于同步信号的种类数,并且同步信号检测器相对于彼此并联设置。 每个同步信号检测器检测特定的同步信号。 当在同步信号检测器中检测到用于识别预定码的同步信号并提供给数据传送电路时,提供给数据传送电路的代码中的预定代码中的数据被传送到数据传送电路。
    • 6. 发明授权
    • Digital video signal reproducing apparatus
    • 数字视频信号再现装置
    • US4613908A
    • 1986-09-23
    • US523770
    • 1983-08-16
    • Nobuaki TakahashiSeiichi TakashimaTakeshi ShibamotoKoji TanakaFujio SuzukiMitsuo KuboMitsuru KikuchiHiroyuki SugiyamaYoshiaki Amano
    • Nobuaki TakahashiSeiichi TakashimaTakeshi ShibamotoKoji TanakaFujio SuzukiMitsuo KuboMitsuru KikuchiHiroyuki SugiyamaYoshiaki Amano
    • H04N9/79H04N9/804H04N5/76
    • H04N9/804H04N9/7925G11B2220/20
    • A digital video signal reproducing apparatus comprises a reproducing circuit for reproducing a digital video signal from a recording medium, where the recording medium is time-sequentially recorded with the digital video signal having a signal format in which a header signal is added to each of divided picture element data groups which are obtained by dividing a picture element data group in terms of a predetermined unit, the picture element data group is obtained by subjecting an analog video signal to a digital pulse modulation at a sampling frequency such that a product of a number of picture element data in one scanning line and an effective number of scanning lines in one picture of a standard television system is exceedingly close to 2.sup.18 but less than 2.sup.18, and the header signal at least comprises a synchronizing signal and a picture mode identification code, a header signal reproducing circuit for discriminating the header signal within the digital video signal reproduced by the reproducing circuit and reproducing the header signal, two memory circuits into which the picture element data group within said reproduced digital video signal is written and from which a stored picture element data group is read out, a circuit for controlling write-in and read-out with respect to the two memory circuits according to a code in the reproduced header signal, and a circuit for producing an analog video signal in accordance with a standard television system from the picture element data read out from the two memory circuits.
    • 数字视频信号再现装置包括一个再现电路,用于从记录介质再现数字视频信号,其中记录介质被时间顺序地记录有数字视频信号,该数字视频信号具有一个信号格式,其中标题信号被添加到每个划分的信号 通过以预定单位划分图像元素数据组而获得的图像元素数据组,通过使模拟视频信号以采样频率进行数字脉冲调制获得,使得数字 一个扫描线中的图像元素数据和标准电视系统的一个图像中的有效数量的扫描线非常接近218但小于218,并且标题信号至少包括同步信号和图像模式识别码, 一个标题信号再现电路,用于鉴别该数字视频信号内的标题信号 再现电路并再现标题信号,写入所述再现的数字视频信号内的图像元素数据组并读出存储的图像元素数据组的两个存储电路,用于控制写入和读出的电路 相对于根据再现的标题信号中的代码的两个存储器电路,以及根据从两个存储器电路读出的像素数据根据标准电视系统产生模拟视频信号的电路。
    • 7. 发明授权
    • Address signal generating circuit for a memory circuit
    • 用于存储电路的地址信号发生电路
    • US4587558A
    • 1986-05-06
    • US540553
    • 1983-10-11
    • Hiroyuki SugiyamaNobuaki TakahashiTakeshi ShibamotoHideo SatoYoshiaki AmanoKoji Tanaka
    • Hiroyuki SugiyamaNobuaki TakahashiTakeshi ShibamotoHideo SatoYoshiaki AmanoKoji Tanaka
    • G11B3/00G06F12/02G11B7/00G11B7/004G11B20/10G11B27/30G11C8/00H04N1/21H04N5/781H04N5/907H04N9/806H04N9/81H04N5/14
    • G06F12/0207G11B27/3027H04N1/21H04N5/907H04N9/8066H04N9/81
    • An address signal generating circuit for a memory circuit comprises a first latch driver for producing a signal corresponding to upper m bits of a 2m-bit address signal which is to be generated, where m is an integer, a second latch driver for producing a signal corresponding to lower m bits of the 2m-bit address signal, a circuit for dividing a 2m-bit signal which has a predetermined value into upper m bits and lower m bits and for alternately producing signals corresponding to the upper and lower m bits, a first adder for adding the value of n bits in the signal which has the predetermined value and the value of upper n bits in an output signal of the first or second latch driver and for producing an n-bit signal, where n is an integer less than m, a second adder for adding the value of m-n bits in the signal which has the predetermined value and lower m-n bits of the output signal of the first or second latch driver and for producing an (m-n)-bit signal, an adding circuit for supplying a carry signal of the first or second adder to the second or the first adder so as to add the carry signal with another input signal of the second or the first adder, and a driver control circuit for controlling the first and second latch drivers to alternately and time-divisionally produce upper m bits of the 2m-bit address signal and lower m bits of the 2m-bit address signal by alternately latching an m-bit output signal of the first and second adders in the first and second latch drivers.
    • 一种用于存储电路的地址信号产生电路包括:第一锁存驱动器,用于产生对应于要生成的2m位地址信号的高m位的信号,其中m是整数;第二锁存驱动器,用于产生信号 对应于2m位地址信号的较低m位,用于将具有预定值的2m位信号划分为上m位和低m位并用于交替产生对应于上m位和下m位的信号的电路, 第一加法器,用于将具有预定值的信号中的n位的值和第一或第二锁存驱动器的输出信号中的高n位的值相加,并产生n位信号,其中n是整数减去 m的第二加法器,用于将具有第一或第二锁存驱动器的输出信号的预定值和较低mn位的信号中的mn位的值相加并用于产生(mn)位信号;第二加法器, 供应 将第一或第二加法器的进位信号输入到第二加法器或第一加法器,以将进位信号与第二加法器或第一加法器的另一输入信号相加,以及驱动器控制电路,用于将第一和第二锁存驱动器控制为 通过交替地锁存第一和第二锁存驱动器中的第一和第二加法器的m位输出信号,交替地并且分时地产生2m位地址信号的高位m位和2m位地址信号的较低位。
    • 8. 发明授权
    • Digital video signal reproducing apparatus
    • 数字视频信号再现装置
    • US4614979A
    • 1986-09-30
    • US530033
    • 1983-09-07
    • Hiroyuki SugiyamaYoshiaki AmanoRyozo AbeNobuaki TakahashiTakeshi ShibamotoHideo SatoKoji Tanaka
    • Hiroyuki SugiyamaYoshiaki AmanoRyozo AbeNobuaki TakahashiTakeshi ShibamotoHideo SatoKoji Tanaka
    • H04N5/93H04N5/907H04N5/92H04N9/877H04N5/91
    • H04N9/877
    • A digital video signal reproducing apparatus comprises a reproducing circuit for reproducing a digital video signal from a recording medium, which digital video signal is added with at least a write-in specifying code and a read-out specifying code for specifying a memory circuit part to picture element data groups which are obtained by subjecting a video signal to a digital pulse modulation, a detecting circuit for detecting the write-in specifying code and the read-out specifying code within a reproduced digital video signal from the reproducing circuit, a generator for generating various synchronizing signals and reference signals, first and second memory circuit parts each having a memory capacity for storing picture element data corresponding to one picture, a write controller for causing the picture element data to be written into one of the first and second memory circuit parts according to a value of the write-in specifying code, a latch circuit for latching the read-out specifying code by a vertical synchronizing signal generated from the generator, a read controller for causing stored picture element data to be successively read out from one of the first and second memory circuit parts according to a value of the read-out specifying code from the latch circuit, and a circuit for converting the picture element data read out from the first and second memory circuit parts to an analog video signal.
    • 数字视频信号再现装置包括一个再现电路,用于从记录介质再现数字视频信号,该数字视频信号至少添加了一个写入指定码和一个用于指定存储器电路部分的读出指定码 通过对视频信号进行数字脉冲调制而获得的图像元素数据组,用于检测来自再现电路的再现的数字视频信号中的写入指定代码和读出指定代码的检测电路, 产生各种同步信号和参考信号,第一和第二存储器电路部件,每个存储器电路部件具有用于存储与一个图像相对应的图像元素数据的存储容量;写入控制器,用于使图像元素数据被写入第一和第二存储器电路之一 根据写入指定码的值的部分,用于锁存读出的规格的锁存电路 通过由发生器产生的垂直同步信号产生一个代码;一个读取控制器,用于根据来自该锁存器的读出指定代码的值从第一和第二存储器电路部件中的一个连续读出存储的图像元素数据; 电路和用于将从第一和第二存储器电路部分读出的像素数据转换为模拟视频信号的电路。
    • 9. 发明授权
    • Digital video signal recording system and reproducing apparatus
    • 数字视频信号记录系统和再现装置
    • US4520401A
    • 1985-05-28
    • US485054
    • 1983-04-14
    • Nobuaki TakahashiSeiichi TakashimaTakeshi ShibamotoFujio SuzukiKoji TanakaMitsuo KuboHiroyuki SugiyamaYoshiaki AmanoMitsuru Kikuchi
    • Nobuaki TakahashiSeiichi TakashimaTakeshi ShibamotoFujio SuzukiKoji TanakaMitsuo KuboHiroyuki SugiyamaYoshiaki AmanoMitsuru Kikuchi
    • H04N9/79H04N9/804H04N9/877H04N5/76
    • H04N9/877H04N9/7925H04N9/804G11B2220/20
    • A digital video signal recording system and reproducing apparatus comprise a circuit for independently subjecting a luminance signal and two kinds of color difference signals of a color picture information to digital pulse modulation, to produce a digital luminance signal and two kinds of digital color difference signals, a circuit for dividing the digital luminance signal and the two kinds of digital color difference signals into picture element data groups, in terms of specific number of rows or columns which are adjacent on a screen, and adding a header signal at least comprising a synchronizing signal, a picture mode identification code, and a picture information quantity identification code to a beginning position of each of the divided picture element data groups comprising the digital luminance signal and the two kinds of digital color difference signals, to produce a digital video signal having a signal format in which the digital luminance, the two kinds of digital color difference signals, and the header signal are time-sequentially multiplexed, a circuit for recording the digital video signal onto a recording medium, a circuit for writing each of the divided picture element data groups picked up and reproduced from the recording medium into a memory circuit according to codes within the header signal, and a circuit for producing an analog video signal in accordance with a standard television system from picture element data read out from the memory circuit.
    • 数字视频信号记录系统和再现装置包括用于独立地对亮度信号和彩色图像信息的两种色差信号进行数字脉冲调制的电路,以产生数字亮度信号和两种数字色差信号, 根据在屏幕上相邻的特定数量的行或列,将数字亮度信号和两种数字色差信号分割为像素数据组的电路,以及添加至少包括同步信号的标题信号 ,图像模式识别码,以及图像信息量识别码,包括数字亮度信号和两种数字色差信号的每个分割图像元素数据组的开始位置,以产生具有 信号格式其中数字亮度,两种数字色差 并且头信号被时间顺序复用,用于将数字视频信号记录到记录介质上的电路,用于将从记录介质拾取和再现的每个划分的图像元素数据组写入存储电路的电路 根据标题信号中的代码,以及根据从存储器电路读出的图像元素数据根据标准电视系统产生模拟视频信号的电路。
    • 10. 发明授权
    • Memory utilization control system for compressed digital picture data
transmission system
    • 用于压缩数字图像数据传输系统的存储器利用控制系统
    • US4554597A
    • 1985-11-19
    • US548415
    • 1983-11-03
    • Hiroyuki SugiyamaTakeshi ShibamotoHideo SatoTsuneo FurukiMitsuo KuboKoji Tanaka
    • Hiroyuki SugiyamaTakeshi ShibamotoHideo SatoTsuneo FurukiMitsuo KuboKoji Tanaka
    • G11B9/06G11B20/10H04N1/21H04N5/937H04N9/806H04N9/877H04N5/76
    • H04N1/2141H04N1/2112H04N9/8066H04N9/877H04N2101/00
    • An improved memory utilization control system for compressed digital picture data transmission systems, comprises an input terminal coupled to the memory circuit having a capacity of one frame, an address signal generator generating an address signal which successively indicates write-in addresses in first and second memory regions each amounting to one field in the memory circuit when picture element data of frame-transmission to be reproduced in the first and second fields are applied to the input terminal, and for generating two address signals which respectively and successively indicate write-in addresses in the first and second memory regions when picture element data of field-transmission are applied to the input terminal, a write-in pulse generator generating write-in pulses for writing the picture element data into the memory circuit, and a read-out control circuit for reading out stored picture element data from the first memory region during reproduction of the first field, and for reading out stored picture element data from the second memory region during reproduction of the second field, so that a total capacity of the memory circuit required otherwise is reduced drastically.
    • 一种用于压缩数字图像数据传输系统的改进的存储器利用控制系统,包括耦合到具有一帧容量的存储器电路的输入端,产生连续地指示第一和第二存储器中的写入地址的地址信号的地址信号发生器 当在第一和第二场中要再现的帧传输的图像元素数据被施加到输入端时,分别存储在存储器电路中的一个场的区域,并且用于产生分别连续地指示写入地址的两个地址信号 当场传输的图像元素数据被施加到输入端时的第一和第二存储区域,产生用于将像素数据写入存储器电路的写入脉冲的写入脉冲发生器,以及读出控制电路 用于在第一场的再现期间从第一存储区读出存储的像素数据, 并且用于在再现第二场期间从第二存储器区域读出存储的图像元素数据,使得否则需要的存储器电路的总容量急剧减小。