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1. 发明授权

US5204276A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5204276A
公开(公告)日：1993-04-20
申请号：US645313
申请日：1991-01-24
申请人： Hiroomi Nakajima , Nobuyuki Itoh , Hiroyuki Nihira , Eiryo Tsukioka , Kenji Hirakawa , Shin-ichi Taka , Hideki Takada , Yasuhiro Katsumata , Toshio Yamaguchi
发明人： Hiroomi Nakajima , Nobuyuki Itoh , Hiroyuki Nihira , Eiryo Tsukioka , Kenji Hirakawa , Shin-ichi Taka , Hideki Takada , Yasuhiro Katsumata , Toshio Yamaguchi
IPC分类号： H01L21/033 , H01L21/225 , H01L21/285 , H01L21/331
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/2257 , H01L21/28525 , Y10S148/009 , Y10S148/124
摘要： In the method of manufacturing a semiconductor device, a buffer oxide film, an oxidation-resistant film and a first poly-Si film containing a p-type impurity are successively formed to form a laminate structure on the n-type collector region, followed by forming a protective oxide film by CVD. Then, an opening portion reaching the oxidation-resistant film is formed, followed by forming a second protective insulation film to cover the surface of the first poly-Si film exposed at the side wall of the opening portion. The oxidation-resistant film is excessively etched using the protective insulation films as an etching mask so as to expose the buffer oxide film and to form a bore below the first poly-Si film. The exposed buffer oxide film is removed, followed by filling the bore with a second poly-Si film. Then, a heat treatment is performed under an oxidative atmosphere to form a thermal oxide film covering the surface of the second poly-Si film. At the same time, the p-type impurity contained in the first poly-Si film is diffused through the second poly-Si film into the collector region to form a p-type outer base region. Further, a p-type inner base region, n-type emitter region and an emitter electrode are formed.
摘要翻译：在制造半导体器件的方法中，依次形成缓冲氧化膜，耐氧化膜和含有p型杂质的第一多晶硅膜，以在n型集电极区域上形成叠层结构，随后通过CVD形成保护性氧化膜。然后，形成到达抗氧化膜的开口部分，然后形成第二保护绝缘膜以覆盖暴露在开口部分的侧壁处的第一多晶硅膜的表面。使用保护绝缘膜作为蚀刻掩模来过度蚀刻抗氧化膜，以暴露缓冲氧化物膜并在第一多晶硅膜下方形成孔。除去暴露的缓冲氧化物膜，然后用第二多晶硅膜填充孔。然后，在氧化气氛下进行热处理，形成覆盖第二多晶硅膜表面的热氧化膜。同时，包含在第一多晶硅膜中的p型杂质通过第二多晶硅膜扩散到集电区域中，形成p型外基区。此外，形成p型内基区，n型发射极区和发射极。

2. 发明授权

US5244822A Method of fabricating bipolar transistor using self-aligned polysilicon technology 失效
标题翻译：使用自对准多晶硅技术制造双极晶体管的方法
公开(公告)号：US5244822A
公开(公告)日：1993-09-14
申请号：US818275
申请日：1992-01-08
申请人： Hiroyuki Nihira , Nobuyuki Itoh , Hiroomi Nakajima , Eiryo Tsukioka , Toshio Yamaguchi
发明人： Hiroyuki Nihira , Nobuyuki Itoh , Hiroomi Nakajima , Eiryo Tsukioka , Toshio Yamaguchi
IPC分类号： H01L21/266 , H01L21/285 , H01L21/308 , H01L21/3105 , H01L21/3213 , H01L21/331 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/266 , H01L21/28525 , H01L21/308 , H01L21/3105 , H01L21/32137 , H01L29/0804 , H01L29/7322 , Y10S148/011
摘要： In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an active base layer and a collector layer. When a polysilicon film pattern which defines an active base region and serves as a portion of a base electrode is formed on a wafer surface, a surface portion of a photoresist serving as an etching mask is converted to a carbonized layer by ion implantation. When a micronized emitter layer is formed by a polysilicon-emitter technology, ion implantation is performed before deposition of the polysilicon film or an impurity is doped in the polysilicon film simultaneously with deposition, and rapid thermal annealing is performed so as to activate the doped impurity.
摘要翻译：在通过自对准技术制造的具有用于高速LSI的微粉化结构的双极晶体管中，阻挡绝缘膜被掩埋在发射极层周围的部分中，以比在活性基层和收集层。当在晶片表面上形成限定有源基区并用作基极的一部分的多晶硅膜图案时，用作蚀刻掩模的光致抗蚀剂的表面部分通过离子注入转化为碳化层。当通过多晶硅 - 发射体技术形成微粉化的发射极层时，在沉积多晶硅膜之前进行离子注入，或者在沉积时同时在多晶硅膜中掺杂杂质，并进行快速热退火以激活掺杂杂质。

3. 发明授权

US5096842A Method of fabricating bipolar transistor using self-aligned polysilicon technology 失效
标题翻译：使用自对准多晶硅技术制造双极晶体管的方法
公开(公告)号：US5096842A
公开(公告)日：1992-03-17
申请号：US350860
申请日：1989-05-09
申请人： Hiroyuki Nihira , Nobuyuki Itoh , Hiroomi Nakajima , Eiryo Tsukioka , Toshio Yamaguchi
发明人： Hiroyuki Nihira , Nobuyuki Itoh , Hiroomi Nakajima , Eiryo Tsukioka , Toshio Yamaguchi
IPC分类号： H01L21/266 , H01L21/285 , H01L21/308 , H01L21/3105 , H01L21/3213 , H01L21/331 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/266 , H01L21/28525 , H01L21/308 , H01L21/3105 , H01L21/32137 , H01L29/0804 , H01L29/7322 , Y10S148/011 , Y10S148/124
摘要： In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an active base layer and a collector layer. When a polysilicon film pattern which defines an active base region and serves as a portion of a base electrode is formed on a wafer surface, a surface portion of a photoresist serving as an etching mask is converted to a carbonized layer by ion implantation. When a micronized emitter layer is formed by a polysilicon-emitter technology, ion implantation is performed before deposition of the polysilicon film or an impurity is doped in the polysilicon film simultaneously with deposition, and rapid thermal annealing is performed so as to activate the doped impurity.
摘要翻译：在通过自对准技术制造的具有用于高速LSI的微粉化结构的双极晶体管中，阻挡绝缘膜被掩埋在发射极层周围的部分中，以比在活性基层和收集层。当在晶片表面上形成限定有源基区并用作基极的一部分的多晶硅膜图案时，用作蚀刻掩模的光致抗蚀剂的表面部分通过离子注入转化为碳化层。当通过多晶硅 - 发射体技术形成微粉化的发射极层时，在沉积多晶硅膜之前进行离子注入，或者在沉积时同时在多晶硅膜中掺杂杂质，并进行快速热退火以激活掺杂杂质。

4. 发明授权

US4931409A Method of manufacturing semiconductor device having trench isolation 失效
标题翻译：制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US4931409A
公开(公告)日：1990-06-05
申请号：US302915
申请日：1989-01-30
申请人： Hiroomi Nakajima , Nobuyuki Itoh , Hiroyuki Nihira
发明人： Hiroomi Nakajima , Nobuyuki Itoh , Hiroyuki Nihira
IPC分类号： H01L21/334 , H01L21/763
CPC分类号： H01L29/66181 , H01L21/763
摘要： A method of manufacturing a semiconductor device comprising steps of forming a trench on a semiconductor substrate, forming a first film on the surface of the semiconductor substrate so as to have a large thickness on an upper portion of a side surface of the trench, and to have a small thickness on a bottom portion of the trench, selectively doping an impurity in the bottom portion of the trench through a thin portion of the first film formed on the bottom portion of the trench to form an impurity region on the bottom portion of the trench, removing the first film, and forming a second film having an insulating property on the surface of the semiconductor substrate. A dielectric material or conductive material layer is formed in the trench in which the second film is formed on the inner surface. When the dielectric material or the conductive material layer is formed in the trench, a method of this invention can be applied to formation of trench isolation. When the conductive material layer is formed in the trench, this method can be applied formation of a trench capacitor.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成沟槽，在半导体衬底的表面上形成第一膜以在沟槽的侧表面的上部具有大的厚度，并且在沟槽的底部具有小的厚度，通过形成在沟槽的底部上的第一膜的薄部选择性地掺杂沟槽底部的杂质，以在沟槽的底部部分上形成杂质区沟槽，去除第一膜，以及在半导体衬底的表面上形成具有绝缘性能的第二膜。介电材料或导电材料层形成在其中内表面上形成第二膜的沟槽中。当介电材料或导电材料层形成在沟槽中时，本发明的方法可以应用于形成沟槽隔离。当在沟槽中形成导电材料层时，该方法可以应用于形成沟槽电容器。

5. 发明授权

US07629651B2 Semiconductor memory device and manufacturing method therefor 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07629651B2
公开(公告)日：2009-12-08
申请号：US11760401
申请日：2007-06-08
申请人： Hiroomi Nakajima
发明人： Hiroomi Nakajima
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7841 , H01L29/785
摘要： This disclosure concerns a semiconductor memory comprising Fin-type semiconductor layers (Fins) provided on the insulation layer provided on a substrate; first gate insulation films provided on first side surfaces of the Fins; second gate insulation films provided on second side surfaces of the Fins, the second side surfaces being opposite sides of the first side surfaces of the Fins; front gate electrodes provided on the first side surfaces via the first gate insulation films; and back gate electrodes provided between a second side surface of one of the Fins and a second side surface of the other Fin which is adjacent to the one of the Fins, the second side surface of the one of the Fins is opposed to the second side surface of the other Fin, wherein widths of the front gate electrodes or the back gate electrodes are smaller than the feature size (F).
摘要翻译：本公开涉及一种半导体存储器，其包括设置在设置在基板上的绝缘层上的Fin型半导体层（Fins）设置在金属丝的第一侧面上的第一栅极绝缘膜; 设置在所述金属丝的第二侧表面上的第二栅极绝缘膜，所述第二侧表面是所述金属丝的所述第一侧表面的相对侧; 经由所述第一栅极绝缘膜设置在所述第一侧表面上的前栅电极; 以及设置在所述Fins中的一个的第二侧表面和与所述Fins中的一个相邻的另一Fin的第二侧表面的背栅电极，所述一个Fins的第二侧表面与所述第二侧相对另一个Fin的表面，其中前栅电极或后栅电极的宽度小于特征尺寸（F）。

6. 发明授权

US08373288B2 Alignment mark, method of manufacturing semiconductor device, and mask set 有权
标题翻译：对准标记，制造半导体器件的方法和掩模组
公开(公告)号：US08373288B2
公开(公告)日：2013-02-12
申请号：US12726697
申请日：2010-03-18
申请人： Hiroomi Nakajima
发明人： Hiroomi Nakajima
IPC分类号： H01L23/544
CPC分类号： G03F9/7046 , H01L27/2481
摘要： An alignment mark formed by using a first mask used in forming a same memory cell pattern on a substrate and formed together with the memory cell pattern includes: a first pattern for position detection used for alignment in forming a first wiring pattern; and a first irregular reflection prevention mark that suppresses, when a position detection signal is irradiated as alignment in forming a second wiring pattern further on an upper layer side than the first wiring pattern, irregular reflection of a position detection signal from a second pattern for position detection formed further in a lower layer than the first pattern for position detection.
摘要翻译：通过使用用于在基板上形成相同存储单元图形并与存储单元图案一起形成的第一掩模形成的对准标记包括：用于在形成第一布线图案时进行对准的位置检测用的第一图案; 以及第一不规则反射防止标记，当位置检测信号在比第一布线图案的上层侧进一步形成第二布线图案时，抑制位置检测信号作为对准而被照射，位置检测信号从位置的第二图案不规则地反射在比用于位置检测的第一图案的下层更进一步形成检测。

7. 发明申请

US20050167751A1 Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same 失效
标题翻译：半导体存储装置，用于将数据存储为在通道体中累积的多数载流子的状态及其制造方法
公开(公告)号：US20050167751A1
公开(公告)日：2005-08-04
申请号：US10994629
申请日：2004-11-23
申请人： Hiroomi Nakajima , Kazumi Inoh
发明人： Hiroomi Nakajima , Kazumi Inoh
IPC分类号： H01L27/108 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/788 , H01L29/76
CPC分类号： H01L29/66825 , G11C16/04 , G11C16/3431 , H01L21/28273 , H01L21/84 , H01L27/1203 , H01L29/7841 , H01L29/7881
摘要： A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistor operative to write data in the memory transistor.
摘要翻译：半导体存储器件包括衬底; 通过绝缘体层从衬底隔离的第一导电类型的半导体层; 具有形成在半导体层中的第二导电类型的栅电极，漏极和源极区的存储晶体管，以及形成在该区域之间的半导体层中的第一导电类型的沟道体，存储晶体管用于存储数据作为多数航空母舰积聚在通道体内的状态; 所述第一导电类型的杂质扩散区域形成在与所述漏极区域的上表面接触的位置处，所述杂质扩散区域具有比所述第二导电类型的杂质浓度高的第一导电类型的杂质浓度漏区; 以及写入晶体管，其包括具有杂质扩散区域作为发射极区域的双极晶体管，漏极区域作为基极区域，沟道体作为集电极区域，写入晶体管可操作以将数据写入存储晶体管。

8. 发明授权

US07714388B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07714388B2
公开(公告)日：2010-05-11
申请号：US11563889
申请日：2006-11-28
申请人： Hiroomi Nakajima
发明人： Hiroomi Nakajima
IPC分类号： H01L27/12
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/1203 , H01L29/785
摘要： This discloser concerns a semiconductor device including an insulation layer; a FIN-type semiconductor layer provided on the insulation layer and including a floating body region in an electrically floating state and including a source region and a drain region at both sides of the floating body region; gate insulation films provided on both side surfaces of the floating body region; gate electrodes provided on both side surfaces of the floating body region via the gate insulation films; and a source electrode and a drain electrode respectively contacting with the upper surface of the source region and the drain region, wherein in the cross section of the FIN-type semiconductor layer in parallel with the surface of the insulation layer, a thickness of the FIN-type semiconductor layer in the floating body region is smaller than a thickness of the FIN-type semiconductor layer in the source and the drain regions.
摘要翻译：这一点涉及包括绝缘层的半导体器件; 设置在所述绝缘层上并且包括浮动状态的浮体区域并且包括在所述浮体区域的两侧的源极区域和漏极区域的FIN型半导体层; 设置在浮体区域的两侧面上的栅极绝缘膜; 经由栅极绝缘膜设置在浮体区域的两个侧表面上的栅电极; 以及分别与源极区域和漏极区域的上表面接触的源电极和漏电极，其中在与绝缘层的表面平行的FIN型半导体层的截面中，FIN的厚度在浮体区域中的半导体层的厚度小于源极和漏极区域中的FIN型半导体层的厚度。

9. 发明授权

US07696558B2 Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same 失效
标题翻译：半导体存储装置，用于将数据存储为在通道体中累积的多数载流子的状态及其制造方法
公开(公告)号：US07696558B2
公开(公告)日：2010-04-13
申请号：US11761889
申请日：2007-06-12
申请人： Hiroomi Nakajima , Kazumi Inoh
发明人： Hiroomi Nakajima , Kazumi Inoh
IPC分类号： H01L29/74 , H01L29/80 , H01S3/00
CPC分类号： H01L29/66825 , G11C16/04 , G11C16/3431 , H01L21/28273 , H01L21/84 , H01L27/1203 , H01L29/7841 , H01L29/7881
摘要： A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistor operative to write data in the memory transistor.
摘要翻译：半导体存储器件包括衬底; 通过绝缘体层从衬底隔离的第一导电类型的半导体层; 具有形成在半导体层中的第二导电类型的栅电极，漏极和源极区的存储晶体管，以及形成在该区域之间的半导体层中的第一导电类型的沟道体，存储晶体管用于存储数据作为多数航空母舰积聚在通道体内的状态; 所述第一导电类型的杂质扩散区域形成在与所述漏极区域的上表面接触的位置处，所述杂质扩散区域具有比所述第二导电类型的杂质浓度高的第一导电类型的杂质浓度漏区; 以及写入晶体管，其包括具有杂质扩散区域作为发射极区域的双极晶体管，漏极区域作为基极区域，沟道体作为集电极区域，写入晶体管可操作以将数据写入存储晶体管。

10. 发明授权

US5510647A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5510647A
公开(公告)日：1996-04-23
申请号：US213027
申请日：1994-03-15
申请人： Hiroomi Nakajima , Yasuhiro Katsumata , Hiroshi Iwai , Toshihiko Iinuma , Kazumi Inou , Mitsuhiko Kitagawa , Kouhei Morizuka , Akio Nakagawa , Ichiro Omura
发明人： Hiroomi Nakajima , Yasuhiro Katsumata , Hiroshi Iwai , Toshihiko Iinuma , Kazumi Inou , Mitsuhiko Kitagawa , Kouhei Morizuka , Akio Nakagawa , Ichiro Omura
IPC分类号： H01L21/331 , H01L27/12 , H01L29/73 , H01L29/786 , H01L29/72 , H01L21/82
CPC分类号： H01L29/66265 , H01L27/1203 , H01L29/66242 , H01L29/7317 , H01L29/78654
摘要： A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.
摘要翻译：在具有氧化硅膜的硅衬底上形成双极晶体管。在氧化硅膜上形成具有（100）面的顶面的n型硅层，作为集电体层使用。使用KOH水溶液通过蚀刻在集电体层的端部上形成由（111）面构成的端面。通过外延生长在端面上形成B掺杂的p硅层，并用作基底层。此外，在基极层上形成As掺杂的n硅层，并用作发射极层。电极分别连接到集电极，基极和发射极层。

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