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1. 发明授权

US5452230A Logic circuit synthesizer 失效
标题翻译：逻辑电路合成器
公开(公告)号：US5452230A
公开(公告)日：1995-09-19
申请号：US53007
申请日：1993-04-27
申请人： Hiroyuki Mori , Yoshio Inoue
发明人： Hiroyuki Mori , Yoshio Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A logic circuit synthesizer is disclosed which synthesizes a better dimensioned logic circuit which has improved electrical characteristics. A logic circuit leveling part levels logic circuit data while referring to a leveling dictionary and maintaining logic function frames to thereby output leveled logic circuit data which contains information about logic function frames. The leveled logic circuit data are then given to a logic circuit synthesizing part where they are leveled using a conversion library and considering the information about logic function frames, whereby synthesized logic circuit data are produced. Since the synthesizing is performed in light of the information about logic function frames and what are prescribed in the conversion library a resultant synthesized logic circuit is improved in terms of both electrical characteristics and a dimension accuracy.
摘要翻译：公开了一种逻辑电路合成器，其合成具有改善的电特性的更好尺寸的逻辑电路。逻辑电路调平部分对逻辑电路数据进行电平，同时参考调平字典并维护逻辑功能帧，从而输出包含关于逻辑功能帧的信息的调平逻辑电路数据。然后将调平的逻辑电路数据提供给逻辑电路合成部分，其中它们使用转换库进行调平，并考虑关于逻辑功能帧的信息，从而产生合成逻辑电路数据。由于根据关于逻辑功能帧的信息进行合成，并且在转换库中规定了什么，所以在电特性和尺寸精度方面改进了合成逻辑电路。

2. 发明授权

US6088821A Logic circuit verification device for semiconductor integrated circuit 失效
标题翻译：半导体集成电路逻辑电路验证装置
公开(公告)号：US6088821A
公开(公告)日：2000-07-11
申请号：US041798
申请日：1998-03-13
申请人： Yasuo Moriguchi , Hiroyuki Mori , Yoshio Inoue , Toshinori Inoshita
发明人： Yasuo Moriguchi , Hiroyuki Mori , Yoshio Inoue , Toshinori Inoshita
IPC分类号： G06F17/50 , G01R31/28 , G06F11/00 , G06F13/00
CPC分类号： G06F17/5022
摘要： A logic verification apparatus for a semiconductor integrated circuit classifies a program described in HDL into connection information of a synchronous circuit portion and connection information of a asynchronous circuit portion, converts a portion of the connection information of the asynchronous circuit portion into the connection information of the synchronous circuit portion and increases circuit portions the function of which can be verified by a cycle based simulation/static timing verification unit, thus making it possible to shorten the time for verification.
摘要翻译：半导体集成电路的逻辑验证装置将HDL中描述的程序分类为同步电路部分的连接信息和异步电路部分的连接信息，将异步电路部分的连接信息的一部分转换为异步电路部分的连接信息同步电路部分，并且增加电路部分，其功能可以通过基于循环的模拟/静态定时验证单元来验证，从而可以缩短验证时间。

3. 发明授权

US5418385A Semiconductor devices using potential wells or resistive elements as delay elements and apparatus for forming such devices 失效
标题翻译：使用势阱或电阻元件作为延迟元件的半导体器件和用于形成这种器件的装置
公开(公告)号：US5418385A
公开(公告)日：1995-05-23
申请号：US149357
申请日：1993-11-09
申请人： Hiroyuki Kawamoto , Hiroyuki Mori , Yoshio Inoue
发明人： Hiroyuki Kawamoto , Hiroyuki Mori , Yoshio Inoue
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/173 , H01L27/02
CPC分类号： H01L27/118
摘要： In a semiconductor device, a signal delay element is configured by using resistance and capacitance components included in a region except regions where logic elements for a gate array exist, and the signal delay element is inserted between a logic element for outputting signals and logic elements for receiving the signals and connected to these logic elements. A placing and wiring apparatus for producing the semiconductor device is disclosed.
摘要翻译：在半导体器件中，信号延迟元件通过使用除了存在用于栅极阵列的逻辑元件的区域之外的区域中包括的电阻和电容分量，并且将信号延迟元件插入用于输出信号的逻辑元件和用于接收信号并连接到这些逻辑元件。公开了一种用于制造半导体器件的放置和布线装置。

4. 发明授权

US6075936A Logic circuit simulation apparatus having cycle-based simulator for simulating circuits including multi-cycle paths 失效
标题翻译：逻辑电路仿真装置具有基于循环的模拟器，用于模拟包括多周期路径的电路
公开(公告)号：US6075936A
公开(公告)日：2000-06-13
申请号：US9930
申请日：1998-01-21
申请人： Hiroyuki Mori , Masahiro Taniguchi , Yoshio Inoue
发明人： Hiroyuki Mori , Masahiro Taniguchi , Yoshio Inoue
IPC分类号： G01R31/28 , G06F17/50 , H01L21/82 , G06F9/455
CPC分类号： G06F17/5022
摘要： Where the output delay of a combinational circuit in a logic circuit is defined by a clock cycle count, data transfer means for outputting data delayed in the same number of clock cycles is inserted in a block of a cycle-based simulator. The data transfer means comprises registers or a combination of registers and selectors. The cycle-based simulator may be further arranged to automatically recognize the output delay of a combinational circuit in a target logic circuit. Data transfer means for effecting an output delay in the recognized number of clock cycles is then automatically inserted in a block of the cycle-based simulator.
摘要翻译：在逻辑电路中的组合电路的输出延迟由时钟周期计数定义的情况下，将以相同数量的时钟周期延迟的数据输出的数据传送装置插入到基于循环的仿真器的块中。数据传送装置包括寄存器或寄存器和选择器的组合。可以进一步布置基于周期的模拟器，以自动识别目标逻辑电路中的组合电路的输出延迟。然后，将自动插入到基于循环的模拟器的块中的用于实现所识别的时钟周期数的输出延迟的数据传送装置。

5. 发明授权

US08171446B2 Method for designing a semiconductor device by computing a number of vias, program therefor, and semiconductor device 有权
标题翻译：通过计算多个通孔，其程序和半导体器件来设计半导体器件的方法
公开(公告)号：US08171446B2
公开(公告)日：2012-05-01
申请号：US12511416
申请日：2009-07-29
申请人： Yoshio Inoue
发明人： Yoshio Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78 , H01L23/5286 , H01L24/06
摘要： A method for designing a semiconductor device includes computing a contact resistance value based on an allowable power supply voltage drop set for a second position corresponding to a given region of a second power supply line on a second wiring layer different from a first wiring layer, and computing a number of vias for the given region based on a result of a comparison between a resistance value of a via coupling a first power supply line and the second power supply line and the contact resistance value.
摘要翻译：一种用于设计半导体器件的方法包括：基于对应于与第一布线层不同的第二布线层上的第二电源线的给定区域的第二位置设置的容许电源电压降计算接触电阻值，以及基于耦合第一电源线的通孔的电阻值和第二电源线与接触电阻值之间的比较的结果，计算给定区域的多个通孔。

6. 发明授权

US06938232B2 Floorplanning apparatus deciding floor plan using logic seeds associated with hierarchical blocks 有权
标题翻译：布置规划设备使用与分级块相关联的逻辑种子来确定平面图
公开(公告)号：US06938232B2
公开(公告)日：2005-08-30
申请号：US10320635
申请日：2002-12-17
申请人： Ken Saito , Yoshio Inoue , Kazuhiro Takahashi , Koji Hirakimoto
发明人： Ken Saito , Yoshio Inoue , Kazuhiro Takahashi , Koji Hirakimoto
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5072
摘要： A floorplanning apparatus includes a seed position decision section for deciding a placement position of a logic seed of each hierarchical block; a cell placement section for placing cells belonging to the hierarchical block around the placement position of each logic seed; and a placement region decision section for deciding placement and routing regions of each hierarchical block considering cell placement results produced by the cell placement section.
摘要翻译：布局规划设备包括种子位置决定部分，用于确定每个分级块的逻辑种子的放置位置; 单元放置部，用于将属于分层块的单元放置在每个逻辑种子的放置位置周围; 以及放置区域判定部，其考虑由所述单元放置部生成的单元布置结果，决定各分层块的布局和布线区域。

7. 发明授权

US06844807B2 Home electronics system enabling display of state of controlled devices in various manners 有权
标题翻译：家用电子系统能够以各种方式显示受控设备的状态
公开(公告)号：US06844807B2
公开(公告)日：2005-01-18
申请号：US09782282
申请日：2001-02-14
申请人： Yoshio Inoue , Shinichiro Ohashi
发明人： Yoshio Inoue , Shinichiro Ohashi
IPC分类号： G06F3/048 , G05B15/02 , G05B23/02 , H04M11/00 , H04Q9/00
CPC分类号： G05B15/02 , G05B2219/2642
摘要： A home electronics system enabling rapid execution of remote control of controlled devices includes a home server, a cellular phone connected to the home server via a public line network, and devices to be controlled controlled in response to a signal from the home server. When the user selects via cellular phone an area, a state or a type of the devices to, the home server creates an image of the current state information showing the state of the devices for transmitting to the cellular phone.
摘要翻译：能够快速执行受控设备的远程控制的家庭电子系统包括家庭服务器，经由公共线路网络连接到家庭服务器的蜂窝电话以及响应于来自家庭服务器的信号而被控制的设备。当用户通过蜂窝电话选择区域，状态或设备的类型时，家庭服务器创建表示用于向蜂窝电话发送的设备的状态的当前状态信息的图像。

8. 发明授权

US06691271B1 Built-in self-test apparatus 失效
标题翻译：内置自检装置
公开(公告)号：US06691271B1
公开(公告)日：2004-02-10
申请号：US09590188
申请日：2000-06-09
申请人： Yusuke Kanehira , Toshinori Inoshita , Yoshio Inoue
发明人： Yusuke Kanehira , Toshinori Inoshita , Yoshio Inoue
IPC分类号： G01R3128
CPC分类号： G01R31/318566
摘要： A built-in self-test circuit including a signal generator and operational elements. The operational elements perform arithmetic operations on a test signal value A, generated by the signal generator, to obtain a comparison signal value A which is fundamentally equal to the test signal value A of the signal generator. By comparing the test signal value A with the comparison signal value A, a test result is obtained.
摘要翻译：内置自测电路，包括信号发生器和操作元件。操作元件对由信号发生器生成的测试信号值A执行算术运算，以获得基本上等于信号发生器的测试信号值A的比较信号值A. 通过比较测试信号值A和比较信号值A，得到测试结果。

9. 发明授权

US06654939B2 Method of designing logic circuit, and computer product 失效
标题翻译：设计逻辑电路，计算机产品的方法
公开(公告)号：US06654939B2
公开(公告)日：2003-11-25
申请号：US09987276
申请日：2001-11-14
申请人： Yu Yamamoto , Yoshio Inoue
发明人： Yu Yamamoto , Yoshio Inoue
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G01R31/318342 , G01R31/318541
摘要： A scan flip flop with a selector is inserted into a position on a path where a timing error has occurred, based on timing analysis in a logic BIST mode, so that the path where the timing error has occurred is pipelined.
摘要翻译：基于逻辑BIST模式的定时分析，将具有选择器的扫描触发器插入到发生定时误差的路径上的位置，使得发生定时误差的路径被流水线化。

10. 发明授权

US5729126A Master slice LSI with integrated fault detection circuitry 失效
标题翻译：具有集成故障检测电路的主分片LSI
公开(公告)号：US5729126A
公开(公告)日：1998-03-17
申请号：US757109
申请日：1996-12-02
申请人： Michio Komoda , Yoshio Inoue
发明人： Michio Komoda , Yoshio Inoue
IPC分类号： H01L21/66 , H01L21/82 , H01L27/118 , G01R31/00
CPC分类号： H01L27/118
摘要： A master slice LSI with fault detection circuitry includes a packed transistor area consisting of rows of semiconductor devices packed on a substrate. Parts of the rows are used for providing an application specific integrated circuit (ASIC). Remaining parts of the rows are used for providing fault detection circuitry for finding faulty semiconductor devices. The fault detection circuitry includes shift registers, sense amplifiers, and a decoder. The detection circuitry is provided only for those rows of semiconductor devices used for providing the intended purpose ASIC.
摘要翻译：具有故障检测电路的主分片LSI包括由衬底上的半导体器件行组成的封装晶体管区域。这些行的一部分用于提供专用集成电路（ASIC）。行的剩余部分用于提供用于找到有缺陷的半导体器件的故障检测电路。故障检测电路包括移位寄存器，读出放大器和解码器。检测电路仅用于那些用于提供预定目的ASIC的半导体器件行。

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