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    • 7. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08542519B2
    • 2013-09-24
    • US13035168
    • 2011-02-25
    • Yoshiaki AsaoTakeshi KajiyamaKuniaki Sugiura
    • Yoshiaki AsaoTakeshi KajiyamaKuniaki Sugiura
    • G11C11/02
    • H01L29/82
    • According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.
    • 根据一个实施例,公开了一种半导体存储器件。 该器件包括在第一方向上布置的MOSFET1和MOSFET2,MOSFET1和MOSFET2上方的可变电阻元件(以下称为R1),R1的下端连接到沿第一方向布置的MOSFET1和MOSFET2,MOSFET3和MOSFET4的漏极,可变电阻 元件(以下称为R2),MOSFET3和MOSFET4之上,R2的下端连接到MOSFET3和MOSFET4的漏极。 该器件还包括沿第一方向延伸并连接到MOSFET1和MOSFET2的源极的第一布线,第二布线沿第一方向延伸并连接到MOSFET3和MOSFET4的源极,上电极连接R1的上端和上端 R2和第三布线沿第一方向延伸并连接到上电极。