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1. 发明申请

US20110012231A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110012231A1
公开(公告)日：2011-01-20
申请号：US12891214
申请日：2010-09-27
申请人： Hiroyuki AMISHIRO , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
发明人： Hiroyuki AMISHIRO , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
IPC分类号： H01L29/8605
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译：本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。有源区靠近电阻元件配置。这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

2. 发明授权

US07821078B2 Semiconductor device having resistor elements and method for manufacturing the same 有权
标题翻译：具有电阻元件的半导体器件及其制造方法
公开(公告)号：US07821078B2
公开(公告)日：2010-10-26
申请号：US12007496
申请日：2008-01-11
申请人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译：本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。有源区靠近电阻元件配置。这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

3. 发明授权

US08089136B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08089136B2
公开(公告)日：2012-01-03
申请号：US12891214
申请日：2010-09-27
申请人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译：本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。有源区靠近电阻元件配置。这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

4. 发明申请

US20060175679A1 Semiconductor device and method for manufacturing the same 审中-公开
公开(公告)号：US20060175679A1
公开(公告)日：2006-08-10
申请号：US11384244
申请日：2006-03-21
申请人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

5. 发明授权

US07045865B2 Semiconductor device with resistor elements formed on insulating film 有权
标题翻译：具有形成在绝缘膜上的电阻元件的半导体器件
公开(公告)号：US07045865B2
公开(公告)日：2006-05-16
申请号：US09960495
申请日：2001-09-24
申请人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
IPC分类号： H01L29/76 , H01L29/00 , H01L21/20
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译：本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。有源区靠近电阻元件配置。这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

6. 发明申请

US20080116526A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080116526A1
公开(公告)日：2008-05-22
申请号：US12007496
申请日：2008-01-11
申请人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
IPC分类号： H01L27/06
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译：本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。有源区靠近电阻元件配置。这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

7. 发明授权

US06779160B2 Apparatus, method and pattern for evaluating semiconductor device characteristics 失效
标题翻译：用于评估半导体器件特性的装置，方法和图案
公开(公告)号：US06779160B2
公开(公告)日：2004-08-17
申请号：US10345950
申请日：2003-01-17
申请人： Hiroyuki Amishiro , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Kenji Yamaguchi
IPC分类号： G06F1750
CPC分类号： G01R31/2621 , G01R27/02 , G01R31/2648 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： External resistance Rsd1 is obtained using a first evaluation pattern of MOSFETs having a gate contact length Lgc1 and a channel width W1 each (in steps 100 and 102). External resistance Rsd2 is then acquired by use of a second evaluation pattern of MOSFETs having a gate contact length Lgc2 and a channel width W2 each (in steps 100 and 104). Thereafter, sheet resistance Rsh and overlapping portion resistance Rdsw of the MOSFETs are computed (in step 106) in accordance with the following expressions: Rsh=(W2·Rsd2−W1·Rsd1)/(Lgc2−Lgc1) Rdsw=(W1·Lgc2·Rsd1−W2·Lgc1·Rsd2)/(Lgc2−Lgc1).
摘要翻译：使用具有栅极接触长度Lgc1和沟道宽度W1的MOSFET的第一评估模式（步骤100和102）获得外部电阻Rsd1。然后通过使用具有栅极接触长度Lgc2和沟道宽度W2的MOSFET的第二评估模式（步骤100和104）来获取外部电阻Rsd2。此后，根据以下表达式计算MOSFET的薄层电阻Rsh和重叠部分电阻Rdsw（在步骤106中）：

8. 发明授权

US06407573B1 Device for evaluating characteristic of insulated gate transistor 失效
标题翻译：绝缘栅晶体管特性评估装置
公开(公告)号：US06407573B1
公开(公告)日：2002-06-18
申请号：US09238887
申请日：1999-01-28
申请人： Kenji Yamaguchi , Hiroyuki Amishiro , Yuko Maruyama
发明人： Kenji Yamaguchi , Hiroyuki Amishiro , Yuko Maruyama
IPC分类号： G01R3126
CPC分类号： G01R31/2621 , H01L2924/0002 , H01L2924/00
摘要： A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST1.1). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST1.6). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (&dgr;) which minimizes the standard deviation of the function (F) determined in the step ST1.7 (step ST1.10). A resistance-based method thus extracts an effective channel length and a series resistance with increased accuracy.
摘要翻译：制备具有较长沟道长度并用作基准的晶体管，以及具有较短沟道长度并经受有效沟道长度提取的晶体管（步骤ST1.1）。当栅极过驱动略微改变时，估计总漏极 - 源极电阻的变化大致为零的假想点，掩模沟道长度对总漏极 - 源极电阻平面提取。计算函数（F）的值，其由总漏极 - 源极电阻的变化率与每单位长度的沟道电阻的乘积与掩模沟道长度的变化率之间的差定义在假想点（步骤ST1.6）。具有较短信道长度的晶体管的真实阈值电压由步骤ST1.7中确定的函数（F）的标准偏差最小化的移位量（delta）确定（步骤ST1.10）。因此，基于电阻的方法提高了精确度的有效通道长度和串联电阻。

9. 发明授权

US06518592B1 Apparatus, method and pattern for evaluating semiconductor device characteristics 失效
标题翻译：用于评估半导体器件特性的装置，方法和图案
公开(公告)号：US06518592B1
公开(公告)日：2003-02-11
申请号：US09713338
申请日：2000-11-16
申请人： Hiroyuki Amishiro , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Kenji Yamaguchi
IPC分类号： H01L2358
CPC分类号： G01R31/2621 , G01R27/02 , G01R31/2648 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： External resistance Rsd1 is obtained using a first evaluation pattern of MOSFETs having a gate contact length Lgc1 and a channel width W1 each (in steps 100 and 102). External resistance Rsd2 is then acquired by use of a second evaluation pattern of MOSFETs having a gate contact length Lgc2 and a channel with W2 each (in steps 100 and 104). Thereafter, sheet resistance Rsh and overlapping portion resistance Rdsw of the MOSFETs are computed (in step 106) in accordance with the following expressions: Rsh=(W2Rsd2−W1·Rsd1)/(Lgc2−Lgc1) Rdsw=(W1Lgc2·Rsd1−W2·Lgc1·Rsd2)/(Lgc2−Lgc1)
摘要翻译：使用具有栅极接触长度Lgc1和沟道宽度W1的MOSFET的第一评估模式（步骤100和102）获得外部电阻Rsd1。然后通过使用具有栅极接触长度Lgc2的MOSFET的第二评估模式和各自的沟道（步骤100和104）来获取外部电阻Rsd2。此后，根据以下表达式计算MOSFET的薄层电阻Rsh和重叠部分电阻Rdsw（在步骤106中）：

10. 发明授权

US09172904B2 Information processing apparatus displaying indices of video contents, information processing method and information processing program 有权
标题翻译：信息处理装置显示视频内容的索引，信息处理方法和信息处理程序
公开(公告)号：US09172904B2
公开(公告)日：2015-10-27
申请号：US13360631
申请日：2012-01-27
申请人： Kenji Yamaguchi , Masaki Sato , Hidehito Taniura
发明人： Kenji Yamaguchi , Masaki Sato , Hidehito Taniura
IPC分类号： H04N5/77 , G11B27/10 , H04N9/82
CPC分类号： G11B27/105 , H04N5/772 , H04N9/8227
摘要： In order to quicken switching of indices and reduce the time required for display after switching, a mobile phone includes a video content specifying portion to specify at least one video content, an index element generating portion to generate a thumbnail for a video content when accepting a generation instruction and to stop generation of the thumbnail when accepting a cancellation instruction, an index element generation requesting portion, in response to the event that a video content is specified by the video content specifying portion, to output a generation instruction including identification information identifying the specified video content to the index element generating portion, and a cancellation instructing portion to output a cancellation instruction to stop generation of the thumbnail for the already specified video content when a new video content is specified before completion of generation of the thumbnail for the already specified video content.
摘要翻译：为了加快索引的切换和减少切换后显示所需的时间，移动电话包括指定至少一个视频内容的视频内容指定部分，当接收到视频内容时生成用于视频内容的缩略图的索引元素生成部分响应于由视频内容指定部分指定了视频内容的事件，生成指示，并且在接收到取消指令时停止生成缩略图，索引元素生成请求部分，输出包含识别信息的识别信息的生成指令指定视频内容到索引元素生成部分，以及消除指示部分，在已经指定的缩略图的生成完成之前指定新的视频内容时，输出取消指令以停止生成已经指定的视频内容的缩略图视频内容

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