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1. 发明授权

US06825504B2 Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06825504B2
公开(公告)日：2004-11-30
申请号：US10277152
申请日：2002-10-22
申请人： Hiroyasu Ishizuka , Kousuke Okuyama , Katsuhiko Kubota
发明人： Hiroyasu Ishizuka , Kousuke Okuyama , Katsuhiko Kubota
IPC分类号： H01L2972
CPC分类号： H01L27/0262
摘要： In order to eliminate the difference in ESD resistance caused by polarities of excessive voltages applied to an external terminal and enhance ESD resistance of a semiconductor integrated circuit device to both the positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.
摘要翻译：为了消除由施加到外部端子的过大电压的极性引起的ESD电阻的差异，并且提高半导体集成电路器件对正负过电压的ESD电阻，具有可控硅结构的保护元件，用于保护内部在外部端子和地电位之间设置有来自正过电压的电路和由用于保护内部电路免于负过电压的二极管D1构成的保护元件。

2. 发明授权

US06469325B1 Semiconductor integrated circuit device and its manufacture 失效
标题翻译：半导体集成电路器件及其制造
公开(公告)号：US06469325B1
公开(公告)日：2002-10-22
申请号：US09297513
申请日：1999-05-03
申请人： Hiroyasu Ishizuka , Kousuke Okuyama , Katsuhiko Kubota
发明人： Hiroyasu Ishizuka , Kousuke Okuyama , Katsuhiko Kubota
IPC分类号： H01L2900
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： In order to eliminate a difference in ESD resistance caused by the polarities of excessive voltages applied to an external terminal and enhance the ESD resistance of a semiconductor integrated circuit device to both positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.
摘要翻译：为了消除由施加到外部端子的过大电压的极性引起的ESD电阻的差异，并且提高半导体集成电路器件的正负过电压的ESD电阻，具有可控硅结构的保护元件，用于保护在外部端子和地电位之间设置有来自正过电压的内部电路和由用于保护内部电路免于负过电压的二极管D1构成的保护元件。

3. 发明授权

US07463517B2 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US07463517B2
公开(公告)日：2008-12-09
申请号：US11869564
申请日：2007-10-09
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C16/04 , G11C14/00
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.
摘要翻译：半导体集成电路器件设置在半导体衬底上，并且包括多个字线，多条数据线，以及多个电可编程和可擦除的非易失性存储器单元，分别耦合到多条字线和多条数据线。可擦除非易失性存储单元每个都包括具有浮置栅极的MIS晶体管，该浮置栅极具有耦合到对应的数据线的第一级多晶硅层，源极和漏极，以及由半导体衬底中的半导体区域形成的控制栅极控制门被耦合到对应的字线。

4. 发明申请

US20080037323A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND NONVOLATILE MEMORY ELEMENT 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US20080037323A1
公开(公告)日：2008-02-14
申请号：US11869564
申请日：2007-10-09
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C16/04
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.
摘要翻译：半导体集成电路器件设置在半导体衬底上，并且包括多个字线，多条数据线，以及多个电可编程和可擦除的非易失性存储器单元，分别耦合到多条字线和多条数据线。可擦除非易失性存储单元每个都包括具有浮置栅极的MIS晶体管，该浮置栅极具有耦合到对应的数据线的第一级多晶硅层，源极和漏极，以及由半导体衬底中的半导体区域形成的控制栅极控制门被耦合到对应的字线。

5. 发明授权

US07428167B2 Semiconductor integrated circuit and nonvolatile memory element 失效
公开(公告)号：US07428167B2
公开(公告)日：2008-09-23
申请号：US11430039
申请日：2006-05-09
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C11/34
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

6. 发明授权

US06906954B2 Semiconductor integrated circuit and nonvolatile memory element 失效
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US06906954B2
公开(公告)日：2005-06-14
申请号：US10817820
申请日：2004-04-06
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/28 , H01L21/8247 , H01L27/105 , G11C14/00
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： 0 Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.
摘要翻译：由于上述原因，即使采用诸如单层多晶硅栅极工艺的单层栅极工艺，也可以获得诸如系统LSI的半导体集成电路，其中数据保存能力优异的非易失性存储器被合并并且与DRAM等封装。此外，由于可以形成高可靠性的非易失性存储器，而不需要对诸如标准CMOS制造工艺的现有技术制造工艺增加任何步骤，本发明可以容易地应用于其中非易失性存储器和逻辑LSI或非易失性存储器和DRAM被合并并封装在相同的半导体衬底上。因此，可以在不增加制造成本的情况下提供闪存被合并和打包的系统LSI。

7. 发明授权

US07289361B2 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US07289361B2
公开(公告)日：2007-10-30
申请号：US11432507
申请日：2006-05-12
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C16/04 , G11C14/00
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.
摘要翻译：半导体集成电路器件设置在半导体衬底上，并且包括多个字线，多条数据线，以及多个电可编程和可擦除的非易失性存储器单元，分别耦合到多个字线和多条数据线。可擦除非易失性存储单元每个都包括具有浮置栅极的MIS晶体管，该浮置栅极具有耦合到对应的数据线的第一级多晶硅层，源极和漏极，以及由半导体衬底中的半导体区域形成的控制栅极控制门被耦合到对应的字线。

8. 发明申请

US20060221688A1 Semiconductor integrated circuit and nonvolatile memory element 有权
公开(公告)号：US20060221688A1
公开(公告)日：2006-10-05
申请号：US11432507
申请日：2006-05-12
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

9. 发明授权

US06545311B2 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US06545311B2
公开(公告)日：2003-04-08
申请号：US09942825
申请日：2001-08-31
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (G03) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.
摘要翻译：基于包括一对差分形式的非易失性存储器元件的存储单元的信息保持能力得到改善。构成闪速存储器的非易失性存储元件（130）的结构使得其隧道氧化膜（G03）和浮栅电极（FGT）分别通过利用晶体管的栅极氧化膜（GT2）和栅电极（GT2）形成用于形成在与元件（130）的半导体衬底相同的半导体衬底上的电路。存储单元以2单元/ 1位方案构成，其中一对非易失性存储器元件可以分别连接到一对互补数据线，并且为非易失性存储元件设置彼此不同的阈值电压状态以便差异地读出数据。读出模式中的字线电压被设定为与热平衡状态（初始阈值电压）中的阈值电压基本相等，并且基本上等于低阈值电压值和高阈值的平均值电压值。因此，增强数据保持能力以实现读出故障率的降低。

10. 发明授权

US06528839B2 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US06528839B2
公开(公告)日：2003-03-04
申请号：US09942902
申请日：2001-08-31
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.
摘要翻译：基于包括一对差分形式的非易失性存储器元件的存储单元的信息保持能力得到改善。构成闪速存储器的非易失性存储元件（130）被构造成通过利用晶体管的栅极氧化膜（GT2）和栅电极（GT2）分别形成隧道氧化膜（GO3）和浮栅电极（FGT）用于形成在与元件（130）的半导体衬底相同的半导体衬底上的电路。存储单元以2单元/ 1位方案构成，其中一对非易失性存储器元件可以分别连接到一对互补数据线，并且为非易失性存储元件设置彼此不同的阈值电压状态以便差异地读出数据。读出模式中的字线电压被设定为与热平衡状态（初始阈值电压）中的阈值电压基本相等，并且基本上等于低阈值电压值和高阈值的平均值电压值。因此，增强数据保持能力以实现读出故障率的降低。

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