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1. 发明授权

US5568642A Computer system with easy programming architecture and programming method therefor 失效
标题翻译：计算机系统具有易于编程的架构及编程方法
公开(公告)号：US5568642A
公开(公告)日：1996-10-22
申请号：US608213
申请日：1996-02-28
申请人： Fumio Negoro , Tetsuri Murata , Kozo Sawamura , Junichi Yuki , Hiroshi Murai , Masayasu Onuki , Norihito Ito , Wieguo Jiang , Masako Yonemura
发明人： Fumio Negoro , Tetsuri Murata , Kozo Sawamura , Junichi Yuki , Hiroshi Murai , Masayasu Onuki , Norihito Ito , Wieguo Jiang , Masako Yonemura
IPC分类号： G06F9/44
CPC分类号： G06F8/20
摘要： A new and useful computer system facilitates simplification of computer programs establishing a dedicated computer system adapted to a specific task, and makes it easy to program and to modify already established programs. The simple and easy method for establishing an application adapted dedicated computer system, operable on a plurality of data items for performing a plurality of functional processes for the data items, comprises the steps of establishing a plurality of program segments, each of to is exclusively assigned for one of the data items and has process content exclusively corresponding to one of the functional processes, and establishing a governing program for establishing systematic interrelationships between the program segments for performing a sequence of processes adapted to the dedicated application.
摘要翻译：一个新的和有用的计算机系统有助于简化计算机程序，建立适合特定任务的专用计算机系统，并且使得编程和修改已经建立的程序变得容易。用于建立应用适应的专用计算机系统的简单和容易的方法可在多个数据项上操作以执行数据项的多个功能处理，包括以下步骤：建立多个程序段，每个程序段被专门分配并且具有与功能过程之一完全相对应的处理内容，以及建立用于在用于执行适合该专用应用的一系列处理的程序段之间建立系统相互关系的管理程序。

2. 发明申请

US20120007900A1 FIELD-SEQUENTIAL COLOR LIQUID CRYSTAL DISPLAY AND METHOD FOR DISPLAYING COLORS THEREOF 审中-公开
标题翻译：现场顺序颜色液晶显示器和显示其颜色的方法
公开(公告)号：US20120007900A1
公开(公告)日：2012-01-12
申请号：US13257472
申请日：2010-03-02
申请人： Hiroshi Murai , Kazuo Sekiya , Kazuhiro Wako
发明人： Hiroshi Murai , Kazuo Sekiya , Kazuhiro Wako
IPC分类号： G09G3/36 , G09G5/10
CPC分类号： G09G3/3413 , G02F2001/133622 , G09G2310/0235 , G09G2310/063 , G09G2320/0242 , G09G2320/0261
摘要： A control drive circuit provided in an FSC-LCD comprises an input stage signal processing/controlling circuit (21) which generates a synchronization signal (32) in synchronization with a frame frequency of an input image signal (30) and image data (34); a sequencer (22) which determines the number of color fields in one frame, a color signal to be allocated to each color field, and the output sequence of the allocated color signals and which generates and outputs field designation signals (38, 40) used to designate the color fields corresponding to the output sequence; and an output stage signal processing/controlling circuit (25) which receives image data (36) from the input stage signal processing/controlling circuit (21) and outputs signals to a source driver (13) and a gate driver (14), in accordance with the field designation signal (38) from the sequencer (22).
摘要翻译：设置在FSC-LCD中的控制驱动电路包括输入级信号处理/控制电路（21），与输入图像信号（30）的帧频和图像数据（34）同步地生成同步信号（32） ; 确定一帧中的色域数量的定序器（22），分配给每个色域的彩色信号以及分配的彩色信号的输出序列，并产生和输出使用的场指定信号（38,40）以指定与输出序列相对应的颜色字段; 以及输出级信号处理/控制电路（25），其从输入级信号处理/控制电路（21）接收图像数据（36），并将信号输出到源极驱动器（13）和栅极驱动器（14）根据来自定序器（22）的场指定信号（38）。

3. 发明申请

US20110058979A1 BONDING WIRE 审中-公开
标题翻译：绑线
公开(公告)号：US20110058979A1
公开(公告)日：2011-03-10
申请号：US12740588
申请日：2008-09-11
申请人： Hiroshi Murai , Jun Chiba , Fujio Amada
发明人： Hiroshi Murai , Jun Chiba , Fujio Amada
IPC分类号： C22C5/02
CPC分类号： C22C5/02 , B23K35/3013 , H01L24/02 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/04042 , H01L2224/05624 , H01L2224/43 , H01L2224/45015 , H01L2224/45139 , H01L2224/45144 , H01L2224/45164 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48639 , H01L2224/78301 , H01L2224/78303 , H01L2224/78306 , H01L2224/85045 , H01L2224/85181 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85439 , H01L2224/859 , H01L2924/00011 , H01L2924/01005 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01021 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/0106 , H01L2924/0107 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/01204 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/01071 , H01L2924/00014 , H01L2924/01201 , H01L2924/01202 , H01L2924/01203 , H01L2924/00 , H01L2924/00012 , H01L2924/013 , H01L2924/20752 , H01L2924/00013 , H01L2924/01006
摘要： [Issues to be Solved] Second bonding failures caused by attached oxide of additive elements on high purity Au bonding wire are to be resolved.[Solution Means] Au alloy bonding wires comprising: 5-100 wt ppm Mg, 5-20 wt ppm In, 5-20 wt ppm Al, 5-20 wt ppm Yb, and residual Au of 99.995 wt % purity or higher, and adding 5-20 wt ppm Ca, and for these alloys adding at least one element among 5-20 wt ppm La, 5-20 wt ppm Lu, 5-100 wt ppm Sn, 5-100 wt ppm Sr to the alloy, and/or, moreover, adding 0.01-1.2 wt % Pd to these alloys. Bonding wire, which contains these trace additive elements do not cause a disturbance by accumulated contamination, because of contamination, which formed at ball formation by micro discharge and at the first bonding on the tip of the capillary, transferring to the wire at second bonding.
摘要翻译： [待解决的问题]解决了在高纯度Au接合线上附加元素的附着氧化物引起的第二次接合故障。 [解决方案]包括：5-100重量ppm的Mg，5-20重量ppm的In，5-20重量ppm的Al，5-20重量ppm的Yb和99.995重量％的纯度或更高的残余金，以及添加5-20重量ppm的Ca，对于这些合金，在5-20重量ppm的La，5-20重量ppm的Lu，5-100重量ppm的Sn，5-100重量ppm的Sr中加入至少一种元素，并且 /或此外，向这些合金中添加0.01-1.2重量％的Pd。含有这些微量添加元素的粘合线不会由于污染而引起累积污染的干扰，这是由于通过微量放电在第一次接合而形成的污染，并且在第二次接合时转移到导线。

4. 发明授权

US07825448B2 U-shaped SONOS memory having an elevated source and drain 有权
标题翻译：具有升高的源极和漏极的U形SONOS存储器
公开(公告)号：US07825448B2
公开(公告)日：2010-11-02
申请号：US12192945
申请日：2008-08-15
申请人： Masatomi Okanishi , Yoshihiro Mikasa , Hiroshi Murai
发明人： Masatomi Okanishi , Yoshihiro Mikasa , Hiroshi Murai
IPC分类号： H01L27/108
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial semiconductor layers.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括形成在半导体衬底上的两个外延半导体层，形成在两个外延半导体层的上部的位线以及形成在两个外延半导体层之间的半导体衬底上的电荷存储层。

5. 发明授权

US07645693B2 Semiconductor device and programming method therefor 有权
标题翻译：半导体器件及其编程方法
公开(公告)号：US07645693B2
公开(公告)日：2010-01-12
申请号：US11414647
申请日：2006-04-27
申请人： Hiroshi Murai
发明人： Hiroshi Murai
IPC分类号： H01L21/44
CPC分类号： H01L27/101
摘要： A semiconductor device includes bit lines (14) provided in a semiconductor substrate (10), word lines (16) provided above the bit lines and running in a width direction of the bit lines (14), metal lines (22) provided above the word lines (16) and running in a length direction of the bit lines (14), and bit line contact regions (28) running in the length direction of the word lines (16) and located between word line regions (26) in which a plurality of word lines (16) are disposed. Each of the bit lines (14) is connected with every other metal line (22) in the bit line contact regions (28). It is thus possible to provide a semiconductor device and a fabrication method therefor in which an alignment margin can be ensured between a contact hole (18) and the bit line (14) to enable downsizing of a memory cell.
摘要翻译：半导体器件包括设置在半导体衬底（10）中的位线（14），设置在位线上方并在位线（14）的宽度方向上运行的字线（16），设置在位线字线（16）并在位线（14）的长度方向上运行，位线接触区域（28）在字线（16）的长度方向上行进并位于字线区域（26）之间，设置多个字线（16）。每个位线（14）与位线接触区域（28）中的每隔一个金属线（22）连接。因此，可以提供一种半导体器件及其制造方法，其中可以确保接触孔（18）和位线（14）之间的取向余量以使得存储单元能够减小尺寸。

6. 发明申请

US20070054454A1 Semiconductor device and programming method therefor 有权
标题翻译：半导体器件及其编程方法
公开(公告)号：US20070054454A1
公开(公告)日：2007-03-08
申请号：US11414647
申请日：2006-04-27
申请人： Hiroshi Murai
发明人： Hiroshi Murai
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8242
CPC分类号： H01L27/101
摘要： A semiconductor device includes bit line's (14) provided in a semiconductor substrate (10), word lines (16) provided above the bit lines and running in a width direction of the bit lines (14), metal lines (22) provided above the word lines (16) and running in a length direction of the bit lines (14), and bit line contact regions (28) running in the length direction of the word lines (16) and located between word line regions (26) in which a plurality of word lines (16) are disposed. Each of the bit lines (14) is connected with every other metal line (22) in the bit line contact regions (28). It is thus possible to provide a semiconductor device and a fabrication method therefor in which an alignment margin can be ensured between a contact hole (18) and the bit line (14) to enable downsizing of a memory cell.
摘要翻译：一种半导体器件，包括设置在半导体衬底（10）中的位线（14），设置在位线上方并在位线（14）的宽度方向上运行的字线（16），设置在位线字线（16）并在位线（14）的长度方向上运行，位线接触区域（28）在字线（16）的长度方向上行进并位于字线区域（26）之间，设置多个字线（16）。每个位线（14）与位线接触区域（28）中的每隔一个金属线（22）连接。因此，可以提供一种半导体器件及其制造方法，其中可以确保接触孔（18）和位线（14）之间的取向余量以使得存储单元能够减小尺寸。

7. 发明授权

US07910980B2 Sonos device with insulating storage layer and P-N junction isolation 有权
标题翻译： Sonos器件具有绝缘存储层和P-N结隔离
公开(公告)号：US07910980B2
公开(公告)日：2011-03-22
申请号：US12235321
申请日：2008-09-22
申请人： Hiroshi Murai , Masahiko Higashi
发明人： Hiroshi Murai , Masahiko Higashi
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/11565
摘要： The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO film disposed on each of the bit lines. The film thickness of a first silicon nitride film in the first ONO film is larger than the film thickness of a second silicon nitride film in the second ONO film.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括设置在半导体衬底中的位线，设置在半导体衬底上的位线之间的第一ONO和设置在每个位线上的第二ONO膜。第一ONO膜中的第一氮化硅膜的膜厚度大于第二ONO膜中的第二氮化硅膜的膜厚度。

8. 发明申请

US20100171222A1 HIGH RELIABILITY Au ALLOY BONDING WIRE AND SEMICONDUCTOR DEVICE OF SAME 审中-公开
标题翻译：高可靠性Au合金焊线和半导体器件
公开(公告)号：US20100171222A1
公开(公告)日：2010-07-08
申请号：US12297263
申请日：2008-03-26
申请人： Hiroshi Murai , Jun Chiba , Fujio Amada
发明人： Hiroshi Murai , Jun Chiba , Fujio Amada
IPC分类号： H01L23/49 , H01B5/00
CPC分类号： C22C5/02 , B23K35/0227 , B23K35/3013 , B23K2101/36 , B23K2103/10 , H01L24/02 , H01L24/45 , H01L2224/05624 , H01L2224/45015 , H01L2224/45144 , H01L2224/48011 , H01L2224/4845 , H01L2224/48624 , H01L2224/85201 , H01L2224/859 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/01204 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/20752 , H01L2924/20755 , H01L2924/20656 , H01L2924/013 , H01L2924/00 , H01L2224/43 , H01L2924/01006
摘要： [Issues to be Solved] Providing enhanced bonding reliability of Au alloy bonding wire with low electrical resistivity to Al electrode of semiconductor device, and its application of semiconductor device is bonded with Al electrode pad by the same wire.[Solution Means] Au alloy bonding wire comprising: 0.02-0.3 mass % Ag, total amount of 10-200 mass ppm at least one element of Ge and/or Si, and/or total amount of 10-200 mass ppm at least one element of Al and/or Cu, with residual of Au. Moreover, Al and/or Al alloy pad bonded with the above Au alloy bonding wire.
摘要翻译： [待解决的问题]提供具有低电阻率的Au合金接合线对于半导体器件的Al电极的增强的接合可靠性，并且通过相同的导线将其半导体器件的应用与Al电极焊盘接合。 [解决方案] Au合金接合线包括：0.02-0.3质量％Ag，总量为10-200质量ppm的至少一种Ge和/或Si元素和/或总量为10-200质量ppm的至少一种 Al和/或Cu的元素，残余的Au。此外，与上述Au合金接合线接合的Al和/或Al合金垫。

9. 发明授权

US07736953B2 Semiconductor memory and method of fabricating the same 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US07736953B2
公开(公告)日：2010-06-15
申请号：US11291342
申请日：2005-11-30
申请人： Hiroshi Murai , Masahiko Higashi
发明人： Hiroshi Murai , Masahiko Higashi
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory includes first and second source regions that are formed in a semiconductor substrate and run in orthogonal directions. The first and second source regions are diffused regions and are electrically connected to each other at crossing portions thereof. The semiconductor device may further include drain regions formed in the semiconductor substrate, bit lines that run in the direction in which the second source region runs, and a source line formed above the second source region, wherein a contact between the source line and the second source region is aligned with contacts between the bit lines and drain regions formed in the semiconductor substrate.
摘要翻译：半导体存储器包括形成在半导体衬底中并在正交方向上运行的第一和第二源极区。第一和第二源极区域是扩散区域，并且在其交叉部分彼此电连接。半导体器件还可以包括形成在半导体衬底中的漏极区域，沿着第二源极区域延伸的方向延伸的位线和形成在第二源极区域上方的源极线，其中源极线和第二源极区域之间的接触源极区域与形成在半导体衬底中的位线和漏极区域之间的触点对准。

10. 发明授权

US06492593B2 Gold wire for semiconductor element connection and semiconductor element connection method 失效
标题翻译：用于半导体元件连接的金线和半导体元件连接方法
公开(公告)号：US06492593B2
公开(公告)日：2002-12-10
申请号：US09872651
申请日：2001-05-31
申请人： Hiroshi Murai , Shuichi Mitoma , Takeshi Tokuyama , Mitutomo Motomura
发明人： Hiroshi Murai , Shuichi Mitoma , Takeshi Tokuyama , Mitutomo Motomura
IPC分类号： H01R400
CPC分类号： H01L24/85 , B23K20/007 , C22C5/02 , H01L24/11 , H01L24/13 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/0401 , H01L2224/05624 , H01L2224/1134 , H01L2224/13144 , H01L2224/43 , H01L2224/45015 , H01L2224/45144 , H01L2224/45565 , H01L2224/45694 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/78301 , H01L2224/85045 , H01L2224/85181 , H01L2224/85203 , H01L2224/85205 , H01L2924/00011 , H01L2924/00013 , H01L2924/01005 , H01L2924/01012 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/01057 , H01L2924/01058 , H01L2924/01063 , H01L2924/01064 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/01204 , H01L2924/01205 , H01L2924/14 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/01046 , H01L2924/01082 , H01L2924/0102 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/013 , H01L2924/01004 , H01L2924/01071 , H01L2924/01006 , H01L2924/00012
摘要： A gold wire, for semiconductor element connection, having 5-100 ppm by weight of Ca, 5-100 ppm by weight of Gd, and 1-100 ppm by weight of Y. The gold wire further preferably has 1-100 ppm by weight of at least one of Eu, La, Ce and Lu, as well as 1-100 ppm by weight of at least one of Mg and Ti. The total amount of the added elements being no greater than 200 ppm by weight. The balance being gold and unavoidable impurities. A semiconductor element connection method by ball bonding or bump connection using the gold wire.
摘要翻译：用于半导体元件连接的金线，具有5-100重量ppm的Ca，5-100重量ppm的Gd和1-100重量ppm的Y。金丝还优选具有1-100重量ppm 的Eu，La，Ce和Lu中的至少一种，以及1-100重量ppm的Mg和Ti中的至少一种。添加元素的总量不大于200重量ppm。余量为金和不可避免的杂质。一种半导体元件连接方法，通过使用金线的球接或凸块连接。

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