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1. 发明申请

US20070280031A1 NAND TYPE FLASH MEMORY 有权
标题翻译： NAND型闪存
公开(公告)号：US20070280031A1
公开(公告)日：2007-12-06
申请号：US11749214
申请日：2007-05-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
发明人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
IPC分类号： G11C7/02 , G11C16/04 , G11C8/00 , G11C11/34
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/12 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2211/5646 , G11C2211/5647
摘要： A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.
摘要翻译： NAND型闪速存储器，包括由以矩阵形状排列的多个电子可重写存储单元组成的存储单元阵列;以及数据反转控制单元，判定“1”数据或“0”数据的极性是否为当数据被发送到同时写入数据单元内的多个存储单元时，基于“1”数据和“0”数据的数字被反转，并且反转数据，并且在发送的情况下到存储单元阵列向显示极性反转的数据添加反转标志位。

2. 发明授权

US07518922B2 NAND type flash memory 有权
标题翻译： NAND型闪存
公开(公告)号：US07518922B2
公开(公告)日：2009-04-14
申请号：US11749214
申请日：2007-05-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
发明人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/12 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2211/5646 , G11C2211/5647
摘要： A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.
摘要翻译： NAND型闪速存储器，包括由以矩阵形状排列的多个电子可重写存储单元组成的存储单元阵列;以及数据反转控制单元，判定“1”数据或“0”数据的极性是否为当数据被发送到同时写入数据单元内的多个存储单元时，基于“1”数据和“0”数据的数字被反转，并且反转数据，并且在发送的情况下到存储单元阵列向显示极性反转的数据添加反转标志位。

3. 发明申请

US20090027941A1 SEMICONDUCTOR MEMORY DEVICE WITH POWER SUPPLY WIRING ON THE MOST UPPER LAYER 有权
标题翻译：半导体存储器件，具有在最上层的电源接线
公开(公告)号：US20090027941A1
公开(公告)日：2009-01-29
申请号：US11782311
申请日：2007-07-24
申请人： Hiroshi Maejima , Takumi Abe , Makoto Hamada
发明人： Hiroshi Maejima , Takumi Abe , Makoto Hamada
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C16/0483 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： A memory cell array in a semiconductor substrate has a plurality of memory cells arranged in rows and columns. A first circuit is located at one end of the memory cell array in a column direction. A second circuit is located at the other end of the memory cell array in the column direction. A first wire is located above the memory cell array between the first circuit and the second circuit. The first wire is located in a most upper layer in the semiconductor substrate to supply power to the second circuit.
摘要翻译：半导体衬底中的存储单元阵列具有排列成行和列的多个存储单元。第一电路位于存储单元阵列的列方向的一端。第二电路在列方向上位于存储单元阵列的另一端。第一导线位于第一电路和第二电路之间的存储单元阵列的上方。第一导线位于半导体衬底中的最上层，以向第二电路供电。

4. 发明申请

US20050180213A1 NAND-structured flash memory 有权
标题翻译： NAND结构闪存
公开(公告)号：US20050180213A1
公开(公告)日：2005-08-18
申请号：US11057203
申请日：2005-02-15
申请人： Takumi Abe , Hiroshi Maejima , Koichi Fukuda , Takahiko Hara
发明人： Takumi Abe , Hiroshi Maejima , Koichi Fukuda , Takahiko Hara
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： A NAND-structured flash memory comprises a memory cell array wherein plural memory strings are arranged in matrix form, each of the memory cell strings including plural nonvolatile memory cells, the first conducting paths of the memory cells being connected in series, at least one of the memory cells having a function other than an external data storing function, plural first selection transistors having second conducting paths, and one end of the second conducting paths being connected to one end of the series of the first conducting paths, respectively, plural bit lines connected to the other end of the second conducting paths, plural second selection transistors having third conducting paths, and one end of the third conducting paths being connected to one end of the series of the first conducting paths, respectively, and a source line connected to the other end of the third conducting paths.
摘要翻译： NAND结构的闪速存储器包括其中多个存储器串以矩阵形式布置的存储单元阵列，每个存储单元串包括多个非易失性存储单元，存储单元的第一导电路径串联连接，至少一个所述存储单元具有除了外部数据存储功能之外的功能，多个第一选择晶体管具有第二导电路径，并且所述第二导电路径的一端分别连接到所述一系列第一导电路径的一端，多个位线连接到第二导电路径的另一端，多个具有第三导电路径的第二选择晶体管，并且第三导电路径的一端分别连接到一系列第一导电路径的一端，源极线连接到第三导通路径的另一端。

5. 发明授权

US07590004B2 Nonvolatile semiconductor memory having a plurality of interconnect layers 有权
标题翻译：具有多个互连层的非易失性半导体存储器
公开(公告)号：US07590004B2
公开(公告)日：2009-09-15
申请号：US11345505
申请日：2006-02-02
申请人： Takumi Abe , Koichi Fukuda , Hiroshi Maejima
发明人： Takumi Abe , Koichi Fukuda , Hiroshi Maejima
IPC分类号： G11C16/22
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell array including horizontally aligned memory cell columns, each including vertically arranged memory cell transistors and select transistors selecting the memory cell transistors; first cell well lines connecting well regions in which the memory cell columns are formed; second cell well lines arranged in an interconnect layer above the first cell well lines and connecting the first cell well lines to one another electrically; and a cell source line connecting source terminals of the select transistors in each memory cell column.
摘要翻译：非易失性半导体存储器包括存储单元阵列，其包括水平排列的存储单元列，每个存储单元列包括垂直布置的存储单元晶体管和选择存储单元晶体管的连接形成存储单元列的阱区的第一单元阱线; 布置在第一单元阱线上方的互连层中并将第一单元阱线彼此电连接的第二单元阱线; 以及连接每个存储单元列中的选择晶体管的源极的单元源极线。

6. 发明授权

US07542321B2 Semiconductor memory device with power supply wiring on the most upper layer 有权
标题翻译：半导体存储器件，电源接线最上层
公开(公告)号：US07542321B2
公开(公告)日：2009-06-02
申请号：US11782311
申请日：2007-07-24
申请人： Hiroshi Maejima , Takumi Abe , Makoto Hamada
发明人： Hiroshi Maejima , Takumi Abe , Makoto Hamada
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , G11C16/0483 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： A memory cell array in a semiconductor substrate has a plurality of memory cells arranged in rows and columns. A first circuit is located at one end of the memory cell array in a column direction. A second circuit is located at the other end of the memory cell array in the column direction. A first wire is located above the memory cell array between the first circuit and the second circuit. The first wire is located in a most upper layer in the semiconductor substrate to supply power to the second circuit.
摘要翻译：半导体衬底中的存储单元阵列具有排列成行和列的多个存储单元。第一电路位于存储单元阵列的列方向的一端。第二电路在列方向上位于存储单元阵列的另一端。第一导线位于第一电路和第二电路之间的存储单元阵列的上方。第一导线位于半导体衬底中的最上层，以向第二电路供电。

7. 发明授权

US07630261B2 Nand-structured flash memory 有权
标题翻译： Nand结构闪存
公开(公告)号：US07630261B2
公开(公告)日：2009-12-08
申请号：US11770252
申请日：2007-06-28
申请人： Takumi Abe , Hiroshi Maejima , Koichi Fukuda , Takahiko Hara
发明人： Takumi Abe , Hiroshi Maejima , Koichi Fukuda , Takahiko Hara
IPC分类号： G11C7/02
CPC分类号： G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor, a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate, a dummy gate driving circuit controlling a potential of the control gate of the dummy gate, and a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing the external data.
摘要翻译：一种NAND结构的闪速存储器，包括具有第一导电路径的选择晶体管，第一导电路径的一端连接到位线或源极线，至少一个具有第二导电路径和控制栅极的虚拟栅极，一个第二导电路径的端部连接到选择晶体管的第一导电路径的另一端，用于存储外部数据的非易失性存储器链接单元，其包括具有第三导电路径和控制的多个电可擦除/可写非易失性存储单元所述第三导电路径串联连接，所述第三导电路径的一端与所述虚拟栅极的所述第二导电路径的另一端连接，所述虚拟栅极驱动电路控制所述控制栅极的电位所述虚拟栅极和存储单元驱动电路选择性地驱动所述多个非易失性存储单元的控制栅极进行写入，读取或者错误 e位用于存储外部数据的数据。

8. 发明授权

US07239556B2 NAND-structured flash memory 有权
标题翻译： NAND结构闪存
公开(公告)号：US07239556B2
公开(公告)日：2007-07-03
申请号：US11057203
申请日：2005-02-15
申请人： Takumi Abe , Hiroshi Maejima , Koichi Fukuda , Takahiko Hara
发明人： Takumi Abe , Hiroshi Maejima , Koichi Fukuda , Takahiko Hara
IPC分类号： G11C11/34
CPC分类号： G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： A NAND-structured flash memory comprises a memory cell array wherein plural memory strings are arranged in matrix form, each of the memory cell strings including plural nonvolatile memory cells, the first conducting paths of the memory cells being connected in series, at least one of the memory cells having a function other than an external data storing function, plural first selection transistors having second conducting paths, and one end of the second conducting paths being connected to one end of the series of the first conducting paths, respectively, plural bit lines connected to the other end of the second conducting paths, plural second selection transistors having third conducting paths, and one end of the third conducting paths being connected to one end of the series of the first conducting paths, respectively, and a source line connected to the other end of the third conducting paths.
摘要翻译： NAND结构的闪速存储器包括其中多个存储器串以矩阵形式布置的存储单元阵列，每个存储单元串包括多个非易失性存储单元，存储单元的第一导电路径串联连接，至少一个所述存储单元具有除了外部数据存储功能之外的功能，多个第一选择晶体管具有第二导电路径，并且所述第二导电路径的一端分别连接到所述一系列第一导电路径的一端，多个位线连接到第二导电路径的另一端，多个具有第三导电路径的第二选择晶体管，并且第三导电路径的一端分别连接到一系列第一导电路径的一端，源极线连接到第三导通路径的另一端。

9. 发明申请

US20060198196A1 Nonvolatile semiconductor memory having a plurality of interconnect layers 有权
公开(公告)号：US20060198196A1
公开(公告)日：2006-09-07
申请号：US11345505
申请日：2006-02-02
申请人： Takumi Abe , Koichi Fukuda , Hiroshi Maejima
发明人： Takumi Abe , Koichi Fukuda , Hiroshi Maejima
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell array including horizontally aligned memory cell columns, each including vertically arranged memory cell transistors and select transistors selecting the memory cell transistors; first cell well lines connecting well regions in which the memory cell columns are formed; second cell well lines arranged in an interconnect layer above the first cell well lines and connecting the first cell well lines to one another electrically; and a cell source line connecting source terminals of the select transistors in each memory cell column.

10. 发明授权

US07923783B2 Semiconductor memory device having resistance element with two conductors 有权
标题翻译：半导体存储器件具有具有两个导体的电阻元件
公开(公告)号：US07923783B2
公开(公告)日：2011-04-12
申请号：US12408287
申请日：2009-03-20
申请人： Takumi Abe
发明人： Takumi Abe
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L27/10 , H01L29/74 , H01L23/62 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/00 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11 , H01L23/48
CPC分类号： H01L27/105 , H01L27/11526 , H01L28/20 , Y10S257/904
摘要： A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged.
摘要翻译：根据本发明的实施例的半导体存储器件包括：电阻元件，其被构造为具有沿第一方向延伸并连接到第一触点的第一导体; 第二导体，其沿所述第一方向延伸并连接到第二触点; 以及存在于所述第一导体和所述第二导体之间的第一绝缘膜，所述第一绝缘膜还具有开口，在所述开口中布置有连接所述第一导体和所述第二导体的第三导体。

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