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1. 发明授权

US5084752A Semiconductor device having bonding pad comprising buffer layer 失效
标题翻译：具有包含缓冲层的接合片的半导体器件
公开(公告)号：US5084752A
公开(公告)日：1992-01-28
申请号：US538817
申请日：1990-06-15
申请人： Shinichi Satoh , Hiroji Ozaki , Hiroshi Kimura , Wataru Wakamiya , Yoshinori Tanaka
发明人： Shinichi Satoh , Hiroji Ozaki , Hiroshi Kimura , Wataru Wakamiya , Yoshinori Tanaka
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/85205 , H01L24/45 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3025
摘要： A semiconductor device includes a substrate (4) in a periphery of which are formed elements isolating regions. A bonding pad (3) is formed above the elements isolating region, with an isolation layer (7) provided therebetween. An underlying layer (12) having a buffering function is formed on a surface of the bonding pad and the semiconductor substrate. In one aspect of the invention, wherein the elements isolating region is formed of LOCOS film (30), the underlying layer is formed between the bonding pad and the LOCOS film. In another aspect of the invention, the elements isolating region is of a field-shield structure (13, 14), and the underlying layer (12) is formed by separating a part of a gate electrode layer (14) of the field shield into an island. The underlying layer buffers the structure against an external force that is applied on the bonding pad in a bonding processing, to thereby prevent generation of cracks in the semiconductor layer.
摘要翻译：半导体器件包括其周边的衬底（4），其形成有元件隔离区域。在元件隔离区域的上方形成接合焊盘（3），其间设有隔离层（7）。在接合焊盘和半导体衬底的表面上形成具有缓冲功能的下层（12）。在本发明的一个方面，其中元件隔离区由LOCOS膜（30）形成，下层在接合焊盘和LOCOS膜之间形成。在本发明的另一方面，元件隔离区域是场屏蔽结构（13,14），并且下层（12）是通过将场屏蔽的栅极电极层（14）的一部分分成一个岛屿。底层在结合处理中抵抗施加在接合焊盘上的外力缓冲结构，从而防止在半导体层中产生裂纹。

2. 发明授权

US4998161A LDD MOS device having an element separation region having an electrostatic screening electrode 失效
标题翻译：具有具有静电屏蔽电极的元件分离区域的LDD MOS器件
公开(公告)号：US4998161A
公开(公告)日：1991-03-05
申请号：US446560
申请日：1989-12-05
申请人： Hiroshi Kimura , Shinichi Satoh , Hiroji Ozaki , Yoshinori Tanaka , Wataru Wakamiya
发明人： Hiroshi Kimura , Shinichi Satoh , Hiroji Ozaki , Yoshinori Tanaka , Wataru Wakamiya
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/06 , H01L29/40 , H01L29/78
CPC分类号： H01L29/402 , H01L27/10805
摘要： In an element forming region (10) of a semiconductor substrate (1), there are provided a gate electrode (2), sidewall insulating films (4), impurity diffusion regions (5a and 5b) of a lower concentration having their one ends are overlapped with the side sections of the gate electrode (2), and impurity diffusion regions (6a and 6b) of a higher concentration having their one ends are overlapped with the side sections of the sidewall insulating films (4). In an element isolation region (7) of the semiconductor substrate, there are formed an electrostatic screening electrode (31) for element isolation and an insulating film (30) substantially enclosing the electrostatic screening electrode. By employing the electrostatic screening electrode (31) for element isolation in the LDD MOS transistor, there is obtained a semiconductor device of high performance and reliability which is free from intrusion of impurities from the element isolation region.
摘要翻译：在半导体衬底（1）的元件形成区域（10）中，设置有栅电极（2），侧壁绝缘膜（4），具有其一端的较低浓度的杂质扩散区域（5a和5b）与栅极（2）的侧部重叠，并且具有一端的较高浓度的杂质扩散区（6a和6b）与侧壁绝缘膜（4）的侧部重叠。在半导体衬底的元件隔离区域（7）中，形成用于元件隔离的静电屏蔽电极（31）和基本上包围静电屏蔽电极的绝缘膜（30）。通过在LDD MOS晶体管中采用用于元件隔离的静电屏蔽电极（31），可以获得高性能和可靠性的半导体器件，其不会从元件隔离区域侵入杂质。

3. 发明授权

US5459344A Stacked capacitor type semiconductor memory device and manufacturing method thereof 失效
标题翻译：叠层电容器型半导体存储器件及其制造方法
公开(公告)号：US5459344A
公开(公告)日：1995-10-17
申请号：US727783
申请日：1991-07-10
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

4. 发明授权

US5288661A Semiconductor device having bonding pad comprising buffer layer 失效
标题翻译：具有包括缓冲层的焊盘的半导体器件
公开(公告)号：US5288661A
公开(公告)日：1994-02-22
申请号：US796976
申请日：1991-11-25
申请人： Shinichi Satoh , Hiroji Ozaki , Hiroshi Kimura , Wataru Wakamiya , Yoshinori Tanaka
发明人： Shinichi Satoh , Hiroji Ozaki , Hiroshi Kimura , Wataru Wakamiya , Yoshinori Tanaka
IPC分类号： H01L21/60 , H01L23/485 , H01L21/28
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/85205 , H01L24/45 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3025
摘要： A semiconductor device according to the present invention comprises a substrate (4) in a periphery of which formed are elements isolating regions. A bonding pad (3) is formed above the elements isolating region with an isolation layer (7) provided therebetween. An underlying layer (12) having a buffering function is formed on a surface of the bonding pad and the semiconductor substrate. In case the elements isolating region is formed of LOCOS film (30), the underlying layer is formed between the bonding pad and the LOCOS film. In case the elements isolating region is of a field-shield structure (13, 14), the underlying layer (12) is formed by separating a part of a gate electrode layer (14) of the field shield into an island. The underlying layer buffers external force applied on the bonding pad in a bonding processing to prevent generation of cracks in the semiconductor layer.
摘要翻译：根据本发明的半导体器件包括其周围形成有元件隔离区的衬底（4）。在元件隔离区域的上方形成有焊盘（3），隔离层（7）设置在它们之间。在接合焊盘和半导体衬底的表面上形成具有缓冲功能的下层（12）。在元件隔离区域由LOCOS膜（30）形成的情况下，在焊盘和LOCOS膜之间形成下层。在元件隔离区域是场屏蔽结构（13,14）的情况下，通过将场屏蔽体的栅极电极层（14）的一部分分离成岛来形成下层（12）。底层在接合处理中缓冲施加在接合焊盘上的外力，以防止在半导体层中产生裂缝。

5. 发明授权

US5278437A Stacked capacitor type semiconductor memory device and manufacturing method thereof 失效
标题翻译：叠层电容器型半导体存储器件及其制造方法
公开(公告)号：US5278437A
公开(公告)日：1994-01-11
申请号：US947615
申请日：1992-09-21
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

6. 发明授权

US5047817A Stacked capacitor for semiconductor memory device 失效
标题翻译：用于半导体存储器件的堆叠电容器
公开(公告)号：US5047817A
公开(公告)日：1991-09-10
申请号：US364033
申请日：1989-06-09
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

7. 发明授权

US5180683A Method of manufacturing stacked capacitor type semiconductor memory device 失效
标题翻译：叠层电容器型半导体存储器件的制造方法
公开(公告)号：US5180683A
公开(公告)日：1993-01-19
申请号：US727781
申请日：1991-07-10
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor had various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

8. 发明授权

US5097310A Complementary semiconductor device having improved device isolating region 失效
标题翻译：具有改进的器件隔离区域的补充半导体器件
公开(公告)号：US5097310A
公开(公告)日：1992-03-17
申请号：US409379
申请日：1989-09-19
申请人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
发明人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
IPC分类号： H01L21/761 , H01L21/76 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928
摘要： A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.
摘要翻译：具有改进的隔离装置能力的互补半导体器件包括在衬底1的主表面上彼此相邻形成的P阱3和N阱2，形成在主衬底1上的P阱8中的N型杂质层在基板的主表面上形成在N阱9中的P型杂质层，形成在基板主表面上的N阱和P阱71的接合部的N型区域，第一屏蔽电极52，其通过绝缘膜形成在基板的主表面上的N型杂质层8和N型区域71之间，形成在N型区域71和P型杂质层9之间的第二屏蔽电极51，基板的主表面通过绝缘膜。第一屏蔽电极52连接到电位VSS，第二屏蔽电极51和N型区域71连接到电位VCC，使得包括第一屏蔽电极52的N沟道MOS晶体管101不导通，包括第二屏蔽电极的装置不形成场效应晶体管。

9. 发明授权

US5930614A Method for forming MOS device having field shield isolation 失效
标题翻译：用于形成具有场屏蔽隔离的MOS器件的方法
公开(公告)号：US5930614A
公开(公告)日：1999-07-27
申请号：US765771
申请日：1991-09-26
申请人： Takahisa Eimori , Shinichi Satoh , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka
发明人： Takahisa Eimori , Shinichi Satoh , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka
IPC分类号： H01L21/76 , H01L21/765 , H01L29/78 , H01L21/8238
CPC分类号： H01L21/765
摘要： A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions. Since the sidewall oxide film is thick, the impurity regions are not overlapped even by diffusion with a portion where the first conductor is projected on the semiconductor substrate. Thus, a threshold voltage of a field shield transistor comprising the first conductor and the impurity regions on both sides thereof is raised, so that isolation characteristics of the field shield is improved.
摘要翻译：用于场屏蔽和第一绝缘膜的第一导体通过绝缘膜在P型半导体衬底的主表面上依次形成为预定形状。在半导体衬底上形成第三绝缘膜，以覆盖第一导体和第二绝缘膜。第三绝缘膜被各向异性地蚀刻，从而在第一导体的侧壁上形成侧壁绝缘膜。分别用作场效晶体管的栅极的第二和第三导体通过第四绝缘膜形成。利用第一绝缘膜，侧壁氧化物膜，第二导体和第三导体作为掩模将n型杂质注入到半导体衬底的主表面中，并扩散，形成杂质区。由于侧壁氧化物膜厚，因此即使通过第一导体投射在半导体基板上的部分的扩散也不会使杂质区域重叠。因此，包括第一导体和其两侧的杂质区域的场屏蔽晶体管的阈值电压升高，从而提高了场屏蔽的隔离特性。

10. 发明授权

US5521419A Semiconductor device having field shield element isolating structure and method of manufacturing the same 失效
标题翻译：具有场屏蔽元件隔离结构的半导体器件及其制造方法
公开(公告)号：US5521419A
公开(公告)日：1996-05-28
申请号：US327341
申请日：1994-10-21
申请人： Wataru Wakamiya , Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka
发明人： Wataru Wakamiya , Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka
IPC分类号： H01L21/76 , H01L21/8242 , H01L23/528 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/76
CPC分类号： H01L27/10852 , H01L23/5283 , H01L27/10808 , H01L2924/0002
摘要： A field shield isolating structure forms a structure for isolating elements of a semiconductor device. The field shield isolating structure includes a field shield gate insulating film and field shield electrode formed on the semiconductor substrate in separate processes to constitute a quasi-MOS transistor using impurity regions of adjacent MOS transistors. The film thickness of the field shield gate insulating film is set arbitrarily, the threshold voltage of the quasi-MOS transistor is set high, and then elements are insulated and isolated, so that the transistor is operated in the off state. The upper surface of the field shield electrode is also covered with the upper insulating film. The thicknesses of the upper insulating film and of the field shield gate insulating film is adjusted to have such values that prevent turning ON of the MOS transistor by the capacitance divided voltage. The voltage may be applied from upper conductive layers such as word lines formed above the upper insulating film.
摘要翻译：场屏蔽隔离结构形成用于隔离半导体器件的元件的结构。场屏蔽隔离结构包括在单独的工艺中形成在半导体衬底上的场屏蔽栅极绝缘膜和场屏蔽电极，以使用相邻MOS晶体管的杂质区构成准MOS晶体管。场屏蔽栅极绝缘膜的膜厚度是任意设定的，准MOS晶体管的阈值电压被设定为高，然后元件被绝缘和隔离，使晶体管工作在关闭状态。场屏蔽电极的上表面也被上绝缘膜覆盖。将上绝缘膜和场屏蔽栅极绝缘膜的厚度调整为具有防止MOS晶体管导通的电容分压的值。可以从形成在上绝缘膜上方的字线等上导电层施加电压。

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