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1. 发明授权

US08912054B2 Thin-film semiconductor device and method of manufacturing the same 有权
标题翻译：薄膜半导体器件及其制造方法
公开(公告)号：US08912054B2
公开(公告)日：2014-12-16
申请号：US13440320
申请日：2012-04-05
申请人： Hiroshi Hayashi , Takahiro Kawashima , Genshiro Kawashi
发明人： Hiroshi Hayashi , Takahiro Kawashima , Genshiro Kawashi
IPC分类号： H01L21/84 , H01L21/20 , H01L21/31 , H01L29/66
CPC分类号： H01L29/66765
摘要： A method of manufacturing a thin-film semiconductor device according to the present disclosure includes: preparing a substrate; forming a gate electrode above the substrate; forming a first insulating film on the gate electrode; forming a semiconductor thin film that is to be a channel layer, on the first insulating film; forming a second insulating film on the semiconductor thin film; irradiating the second insulating film with a beam so as to increase a transmittance of the second insulating film; and forming a source electrode and a drain electrode above the channel layer.
摘要翻译：根据本公开的制造薄膜半导体器件的方法包括：制备衬底; 在所述衬底上形成栅电极; 在栅电极上形成第一绝缘膜; 在所述第一绝缘膜上形成作为沟道层的半导体薄膜; 在所述半导体薄膜上形成第二绝缘膜; 用光束照射第二绝缘膜，以增加第二绝缘膜的透射率; 以及在沟道层上方形成源电极和漏电极。

2. 发明授权

US08330166B2 Thin-film semiconductor device for display apparatus thereof and manufacturing method thereof 有权
标题翻译：显示装置用薄膜半导体装置及其制造方法
公开(公告)号：US08330166B2
公开(公告)日：2012-12-11
申请号：US13115409
申请日：2011-05-25
申请人： Hiroshi Hayashi , Takahiro Kawashima , Genshiro Kawachi
发明人： Hiroshi Hayashi , Takahiro Kawashima , Genshiro Kawachi
IPC分类号： H01L27/14 , H01L29/04 , H01L29/10 , H01L21/00
CPC分类号： H01L29/78696 , H01L29/04 , H01L29/66765
摘要： A thin-film semiconductor device includes, in order, a substrate, a gate electrode, a gate insulating film, a first channel layer, and a second channel layer. The second channel layer includes a protrusion between first top surface end portions. The protrusion has first lateral surfaces that each extend between one of the first top surface end portions and a top surface of the protrusion. An insulation layer is on the top surface of the protrusion. The insulation layer has second lateral surfaces that each extend to one of second top surface end portions of the insulation layer. Two contact layers are each on one of the second top surface end portions of the insulation layer, adjacent one of the second lateral surfaces of the insulation layer, adjacent one of the first lateral surfaces of the protrusion, and on one of the first top surface end portions of the second channel layer. A source electrode is on one of the two contact layers, and a drain electrode is on the other of the two contact layers. The two contact layers and the upper portion of the protrusion of said second channel layer are of opposite conductivity types.
摘要翻译：薄膜半导体器件依次包括衬底，栅电极，栅极绝缘膜，第一沟道层和第二沟道层。第二通道层包括在第一顶表面端部之间的突起。突起具有第一侧表面，每个侧表面在第一顶表面端部之一和突起的顶表面之间延伸。绝缘层位于突起的顶表面上。绝缘层具有第二侧表面，每个侧表面延伸到绝缘层的第二顶表面端部中的一个。两个接触层分别位于绝缘层的第二顶表面端部中的一个上，邻近绝缘层的第二侧表面之一，邻近凸起的第一侧表面之一，并且在第一顶表面第二通道层的端部。源电极位于两个接触层之一上，漏电极位于两个接触层中的另一个上。所述第二通道层的两个接触层和突起的上部具有相反的导电类型。

3. 发明授权

US09000437B2 Thin-film semiconductor device including a multi-layer channel layer, and method of manufacturing the same 有权
标题翻译：包括多层沟道层的薄膜半导体器件及其制造方法
公开(公告)号：US09000437B2
公开(公告)日：2015-04-07
申请号：US13425879
申请日：2012-03-21
申请人： Hiroshi Hayashi , Takahiro Kawashima , Genshirou Kawachi
发明人： Hiroshi Hayashi , Takahiro Kawashima , Genshirou Kawachi
IPC分类号： H01L29/04 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66765 , H01L29/04 , H01L29/78669 , H01L29/78696
摘要： A thin-film semiconductor device according to the present disclosure includes: a substrate; a gate electrode formed above the substrate; a gate insulating film formed on the gate electrode; a channel layer that is formed of a polycrystalline semiconductor layer on the gate insulating film; an amorphous semiconductor layer formed on the channel layer and having a projecting shape in a surface; and a source electrode and a drain electrode that are formed above the amorphous semiconductor layer, and a first portion included in the amorphous semiconductor layer and located closer to the channel layer has a resistivity lower than a resistivity of a second portion included in the amorphous semiconductor layer and located closer to the source and drain electrodes.
摘要翻译：根据本公开的薄膜半导体器件包括：衬底; 形成在所述衬底上的栅电极; 形成在栅电极上的栅极绝缘膜; 在所述栅极绝缘膜上由多晶半导体层形成的沟道层; 形成在所述沟道层上且在表面具有突出形状的非晶半导体层; 以及形成在非晶半导体层上方的源电极和漏电极，并且包括在非晶半导体层中并且位于更靠近沟道层的第一部分的电阻率低于包含在非晶半导体中的第二部分的电阻率并且更靠近源电极和漏电极。

4. 发明授权

US09048220B2 Method of crystallizing silicon thin film and method of manufacturing silicon thin-film transistor device 有权
标题翻译：硅薄膜的结晶方法和硅薄膜晶体管器件的制造方法
公开(公告)号：US09048220B2
公开(公告)日：2015-06-02
申请号：US13228804
申请日：2011-09-09
申请人： Tomohiko Oda , Takahiro Kawashima
发明人： Tomohiko Oda , Takahiro Kawashima
IPC分类号： H01L21/00 , H01L21/84 , H01L29/423 , H01L29/66 , H01L29/786 , H01L27/12
CPC分类号： H01L29/42384 , H01L27/1281 , H01L27/1285 , H01L29/66765 , H01L29/78678
摘要： A method of crystallizing a silicon thin film, which enables uniforming the size of a crystalline grain of the silicon thin film, includes: a second process of stacking, on a substrate, a first gate electrode having a first reflectivity; a third process of stacking a second gate electrode on the first gate electrode, the second gate electrode having a second reflectivity lower than the first reflectivity and including a top face having an area smaller than an area of the top face of the first gate electrode; a fourth process of stacking a gate insulation film to cover a first region and a second region; a fifth process of stacking a noncrystalline silicon thin film on the stacked gate insulation film; and a sixth process of crystallizing the noncrystalline silicon thin film by irradiating the noncrystalline silicon thin film from above with a laser beam.
摘要翻译：使硅薄膜的晶粒尺寸均匀化的硅薄膜的结晶方法包括：在基板上堆叠具有第一反射率的第一栅电极的第二工序; 在所述第一栅电极上层叠第二栅电极的第三工序，所述第二栅电极具有比所述第一反射率低的第二反射率，并且包括具有小于所述第一栅电极的顶面的面积的面的顶面; 堆叠栅极绝缘膜以覆盖第一区域和第二区域的第四工艺; 堆叠栅极绝缘膜上的非晶硅薄膜的第五工序; 以及通过用激光束从上方照射非晶硅薄膜来使非晶硅薄膜结晶的第六工序。

5. 发明申请

US20130001572A1 DISPLAY DEVICE, THIN-FILM TRANSISTOR USED FOR DISPLAY DEVICE, AND METHOD OF MANUFACTURING THIN-FILM TRANSISTORS 审中-公开
标题翻译：显示装置，用于显示装置的薄膜晶体管，以及制造薄膜晶体管的方法
公开(公告)号：US20130001572A1
公开(公告)日：2013-01-03
申请号：US13616673
申请日：2012-09-14
申请人： Eiichi SATOH , Genshirou Kawachi , Takahiro Kawashima
发明人： Eiichi SATOH , Genshirou Kawachi , Takahiro Kawashima
IPC分类号： H01L27/15 , H01L21/336
CPC分类号： H01L27/1248 , H01L29/41733 , H01L29/66765 , H01L29/78606 , H01L29/78696
摘要： A thin-film transistor used for a display device includes a gate electrode formed on an insulating substrate; a gate insulating film formed on the substrate so as to cover the gate electrode; a semiconductor layer composed of first semiconductor layer and second semiconductor layer formed on the gate insulating film; an ohmic contact layer formed on the semiconductor layer; and a source electrode and a drain electrode formed on the ohmic contact layer so as to be spaced from each other. The transistor further includes an etching stopper made of spin-on glass (SOG) on a channel-forming region of the semiconductor layer.
摘要翻译：用于显示装置的薄膜晶体管包括形成在绝缘基板上的栅电极; 栅极绝缘膜，形成在所述基板上以覆盖所述栅电极; 由形成在所述栅极绝缘膜上的第一半导体层和第二半导体层构成的半导体层; 形成在半导体层上的欧姆接触层; 以及形成在欧姆接触层上以彼此间隔开的源电极和漏电极。晶体管还包括在半导体层的沟道形成区上由旋涂玻璃（SOG）制成的蚀刻停止层。

6. 发明授权

US08106382B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08106382B2
公开(公告)日：2012-01-31
申请号：US12305824
申请日：2007-06-18
申请人： Tohru Saitoh , Takahiro Kawashima
发明人： Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L29/66
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/068 , H01L29/41733 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A source electrode 105 which is connected to a portion of at least one semiconductor nanostructure 103 among a plurality of semiconductor nanostructures, a drain electrode 106 connected to another portion of the semiconductor nanostructure 103, and a gate electrode 102 capable of controlling electrical conduction of the semiconductor nanostructure 103 are included. The semiconductor nanostructures 103 include a low concentration region 108 having a relatively low doping concentration and a pair of high concentration regions 107 having a higher doping concentration than that of the low concentration region 108 and being connected to both ends of the low concentration region 108. The doping concentration of the high concentration regions 107 is 1×1019 cm−3 or more; the length of the low concentration region 108 is shorter than a length of the gate electrode 102 along a direction from the source electrode 105 to the drain electrode 106; and the length of the gate electrode 102 is shorter than the interspace between the source electrode 105 and the drain electrode 106.
摘要翻译：连接到多个半导体纳米结构中的至少一个半导体纳米结构103的一部分的源电极105，连接到半导体纳米结构103的另一部分的漏电极106和能够控制半导体纳米结构103的导电的栅电极102 包括半导体纳米结构103。半导体纳米结构103包括具有相对低的掺杂浓度的低浓度区域108和具有比低浓度区域108的掺杂浓度更高的掺杂浓度的一对高浓度区域107并且连接到低浓度区域108的两端。高浓度区域107的掺杂浓度为1×1019cm-3以上; 低浓度区域108的长度比沿源极电极105至漏电极106的方向的栅电极102的长度短; 并且栅电极102的长度比源电极105和漏电极106之间的间隙短。

7. 发明申请

US20110260789A1 VARIABLE GAIN AMPLIFIER CIRCUIT 有权
标题翻译：可变增益放大器电路
公开(公告)号：US20110260789A1
公开(公告)日：2011-10-27
申请号：US12909763
申请日：2010-10-21
申请人： Takahiro Kawashima , Rui Kurihara
发明人： Takahiro Kawashima , Rui Kurihara
IPC分类号： H03F1/34
CPC分类号： H03G1/0088 , G11B7/13 , H03F3/087 , H03F3/45475 , H03F2203/45526
摘要： A variable gain amplifier circuit includes: an operational amplifier having a non-inverting input terminal applied with a predetermined voltage; a feedback resistor having one end connected to an inverting input terminal of the operational amplifier and the other end connected to an output terminal of the operational amplifier; and a variable resistor having one end applied with an input voltage and the other end connected to the inverting input terminal of the operational amplifier.
摘要翻译：可变增益放大器电路包括：具有施加预定电压的非反相输入端的运算放大器; 反馈电阻器，其一端连接到运算放大器的反相输入端子，另一端连接到运算放大器的输出端子; 以及可变电阻器，其一端施加有输入电压，另一端连接到运算放大器的反相输入端。

8. 发明申请

US20110090716A1 DC-DC CONVERTER WITH SNUBBER CIRCUIT 有权
标题翻译：带有SNUBER电路的DC-DC转换器
公开(公告)号：US20110090716A1
公开(公告)日：2011-04-21
申请号：US12999932
申请日：2009-06-15
申请人： Hideki Asuke , Hideharu Takano , Mamoru Tsuruya , Masayoshi Yamamoto , Takahiro Kawashima , Shigeyuki Funabiki
发明人： Hideki Asuke , Hideharu Takano , Mamoru Tsuruya , Masayoshi Yamamoto , Takahiro Kawashima , Shigeyuki Funabiki
IPC分类号： H02M3/335
CPC分类号： H02M3/1584 , H02M1/34 , H02M2001/348
摘要： In order to achieve an object to reduce a surge voltage and suppress noise generation, the present invention provides a DC-DC converter with a snubber circuit, which boosts a voltage Vi of a DC power supply. The snubber circuit includes: a series circuit connected to both ends of a smoothing capacitor Co and including a snubber capacitor Cs and a snubber resistor Rs; a snubber diode Ds1 connected to a node at which the snubber capacitor Cs and the snubber resistor Rs are connected, and to a node at which a reactor Lr1 and an additional winding 1b of a transformer T1 are connected; and a snubber diode Ds2 connected to the node at which the snubber capacitor Cs and the snubber resistor Rs are connected, and to a node at which a reactor Lr2 and an additional winding 2b of a transformer T2 are connected.
摘要翻译：为了实现降低浪涌电压并抑制噪声产生的目的，本发明提供一种具有缓冲电路的DC-DC转换器，其提高DC电源的电压Vi。缓冲电路包括：连接到平滑电容器Co的两端并包括缓冲电容器Cs和缓冲电阻器Rs的串联电路; 连接到缓冲电容器Cs和缓冲电阻器Rs连接的节点的缓冲二极管Ds1以及与变压器T1的电抗器Lr1和附加绕组1b连接的节点; 以及连接到缓冲电容器Cs和缓冲电阻器Rs所连接的节点的缓冲二极管Ds2以及与变压器T2的电抗器Lr2和附加绕组2b连接的节点。

9. 发明申请

US20100224915A1 METHOD FOR PRODUCING SEMICONDUCTOR CHIP, AND FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：用于制造半导体芯片的方法和场效应晶体管及其制造方法
公开(公告)号：US20100224915A1
公开(公告)日：2010-09-09
申请号：US12159352
申请日：2007-01-12
申请人： Takahiro Kawashima , Tohru Saitoh , Tohru Nakagawa , Hideo Torii
发明人： Takahiro Kawashima , Tohru Saitoh , Tohru Nakagawa , Hideo Torii
IPC分类号： H01L29/78 , H01L21/20 , H01L21/336
CPC分类号： H01L27/1266 , H01L21/8221 , H01L27/0688 , H01L27/1203 , H01L27/1285 , H01L27/1292
摘要： According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).
摘要翻译：根据本发明的用于制造半导体片的方法，首先通过在衬底（10）上层叠牺牲层（11）和半导体层（12）来形成至少两个半导体层（12） 10），并重复该堆叠。接下来，通过蚀刻部分牺牲层（11）和部分半导体层（12）将半导体层（12）分割成多个。然后，通过去除牺牲层（11）将片与衬底分离。

10. 发明授权

US07719031B2 Heterojunction biploar transistor and method for manufacturing same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07719031B2
公开(公告)日：2010-05-18
申请号：US10564085
申请日：2004-07-06
申请人： Tohru Saitoh , Takahiro Kawashima , Ken Idota , Yoshihiko Kanzawa , Teruhito Ohnishi
发明人： Tohru Saitoh , Takahiro Kawashima , Ken Idota , Yoshihiko Kanzawa , Teruhito Ohnishi
IPC分类号： H01L29/74
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.
摘要翻译：双极晶体管120包括衬底1，本征基极区域11和非本征基极区域12.本征基极区域11包括由衬底1上形成的硅构成的硅缓冲层109和组成比分级基底层111，其形成在硅缓冲层上并且包含硅并且至少为锗，并且其中锗与硅的组成比在组成比梯度基底层111的厚度方向上变化。外部基极区12包括外部基底形成层113由硅构成，其形成在衬底上并与硅缓冲层相邻。外部基底形成层113的厚度不小于40nm。

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