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    • 1. 发明授权
    • Packet communication system, emission control apparatus, antenna control method and computer program
    • 分组通信系统,排放控制装置,天线控制方法和计算机程序
    • US08937986B2
    • 2015-01-20
    • US13821722
    • 2011-09-07
    • Hiroshi FurukawaOsamu Muta
    • Hiroshi FurukawaOsamu Muta
    • H04B7/17H04B7/155H01Q3/24H01Q9/16H01Q21/24H04B7/10H04B7/06H04B7/08
    • H04B7/15528H01Q3/24H01Q9/16H01Q21/24H04B7/0602H04B7/0802H04B7/10
    • A packet communication system etc., is proposed, which can automatically adjusting the antenna directionality without modifying a wireless interface of a wireless packet forwarding device even if it involves fluctuation in the packet transmission timing due to CSMA/CA etc. An interference evasion unit involves fluctuation in packet transmission timing due to CSMA/CA. A radio emission device can control the emissive direction and/or emission intensity. A packet generation unit adjusts packet features other than its contents (e.g., packet length, transmission intensity) based on a switching sequence for specifying the emissive direction and/or emissive intensity, and generate a switching control packet. An emission control unit measures the switching control packet feature other than its contents, and identifies at least one bit as antenna control information. The emission control unit controls the overall directionality of a directional antenna unit based on a bit sequence including at least one bit thus identified.
    • 提出了一种分组通信系统等,即使涉及由于CSMA / CA等导致的分组发送定时的波动,也能够自动调整天线方向性而不修改无线分组转发装置的无线接口。干扰逃避单元涉及 由于CSMA / CA引起的分组传输时序的波动。 无线电发射装置可以控制发射方向和/或发射强度。 分组产生单元基于用于指定发射方向和/或发射强度的切换序列来调整除其内容之外的分组特征(例如,分组长度,传输强度),并且生成切换控制分组。 排放控制单元测量除了其内容之外的切换控制分组特征,并且将至少一个比特识别为天线控制信息。 排放控制单元基于包括至少一个如此识别的位的比特序列来控制定向天线单元的整体方向性。
    • 2. 发明申请
    • PACKET COMMUNICATION SYSTEM, EMISSION CONTROL APPARATUS, ANTENNA CONTROL METHOD AND COMPUTER PROGRAM
    • 分组通信系统,排放控制装置,天线控制方法和计算机程序
    • US20130272345A1
    • 2013-10-17
    • US13821722
    • 2011-09-07
    • Hiroshi FurukawaOsamu Muta
    • Hiroshi FurukawaOsamu Muta
    • H04B7/155
    • H04B7/15528H01Q3/24H01Q9/16H01Q21/24H04B7/0602H04B7/0802H04B7/10
    • A packet communication system etc., is proposed, which can automatically adjusting the antenna directionality without modifying a wireless interface of a wireless packet forwarding device even if it involves fluctuation in the packet transmission timing due to CSMA/CA etc. An interference evasion unit involves fluctuation in packet transmission timing due to CSMA/CA. A radio emission device can control the emissive direction and/or emission intensity. A packet generation unit adjusts packet features other than its contents (e.g., packet length, transmission intensity) based on a switching sequence for specifying the emissive direction and/or emissive intensity, and generate a switching control packet. An emission control unit measures the switching control packet feature other than its contents, and identifies at least one bit as antenna control information. The emission control unit controls the overall directionality of a directional antenna unit based on a bit sequence including at least one bit thus identified.
    • 提出了一种分组通信系统等,即使涉及由于CSMA / CA等导致的分组发送定时的波动,也能够自动调整天线方向性而不修改无线分组转发装置的无线接口。干扰逃避单元涉及 由于CSMA / CA引起的分组传输时序的波动。 无线电发射装置可以控制发射方向和/或发射强度。 分组产生单元基于用于指定发射方向和/或发射强度的切换序列来调整除其内容之外的分组特征(例如,分组长度,传输强度),并且生成切换控制分组。 排放控制单元测量除了其内容之外的切换控制分组特征,并且将至少一个比特识别为天线控制信息。 排放控制单元基于包括至少一个如此识别的位的比特序列来控制定向天线单元的整体方向性。
    • 5. 发明授权
    • Semiconductor integrated circuit in in a carry computation network having a logic blocks which are dynamically reconfigurable
    • 携带计算网络中的半导体集成电路具有可动态重新配置的逻辑块
    • US08352533B2
    • 2013-01-08
    • US12332673
    • 2008-12-11
    • Hiroshi Furukawa
    • Hiroshi Furukawa
    • G06F7/57
    • G06F7/5443
    • There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner.
    • 提供了一种半导体集成电路,包括:多个可重新配置的第一逻辑块,多个第一逻辑块输入第一位宽的数据并执行计算; 以动态可重新配置的方式连接所述多个第一逻辑块的第一网络; 多个第二逻辑块,输入与第一位宽不同的第二位宽的数据,并执行计算; 连接到所述多个第二逻辑块的输出的第二网络; 以及以动态可重新配置的方式将包括在第一逻辑块中的计算单元的进位位输出连接到包括在第二逻辑块中的计算单元的输入的第三网络。
    • 7. 发明授权
    • Enhanced processor element structure in a reconfigurable integrated circuit device
    • 可重构集成电路设备中增强的处理器元件结构
    • US07734896B2
    • 2010-06-08
    • US11390131
    • 2006-03-28
    • Hiroshi Furukawa
    • Hiroshi Furukawa
    • G06F15/76
    • G06F15/8007
    • A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.
    • 基于配置数据动态地转换任意计算状态的可重构集成电路装置包括多个处理器元件,每个处理器元件具有输入端子,输出端子,并行设置的多个运算单元, 其执行与时钟信号同步的计算处理和以任意状态连接它们的处理器内网络; 以及以任意状态连接处理器元件之间的处理器间网络。 基于配置数据,内部处理器网络可重新配置为期望的连接状态,并且此外,基于配置数据,处理器间网络可重新配置为期望的连接状态。