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1. 发明申请

US20120241834A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120241834A1
公开(公告)日：2012-09-27
申请号：US13234052
申请日：2011-09-15
申请人： Fumiharu Nakajima , Toshiya Kotani , Hiromitsu Mashita , Takafumi Taguchi , Ryota Aburada , Chikaaki Kodama
发明人： Fumiharu Nakajima , Toshiya Kotani , Hiromitsu Mashita , Takafumi Taguchi , Ryota Aburada , Chikaaki Kodama
IPC分类号： H01L27/088 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139 , H01L21/768 , H01L21/76816 , H01L27/0688 , H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11578
摘要： According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.
摘要翻译：根据一个实施例，半导体器件包括从元件形成区域延伸到绘图区域并且与元件形成区域中的半导体元件连接并且与绘图区域中的触点连接的互连。基于在牺牲层的侧表面上匹配第n个（其中n是1或更大的整数）的第一侧壁膜的图案的第（n + 1）第二侧壁膜的图案形成互连。当曝光装置的曝光波长为λ时，在元件形成区域中匹配互连的互连宽度的第一尺寸和元件形成区域中的互连间隔为（k1 / 2n）×（λ/ NA）或更小，透镜的数值孔径的曝光装置为NA，处理参数为k1。在绘图区域中匹配互连间隔的第二维大于第一维度。

2. 发明授权

US08143171B2 Method for manufacturing semiconductor device and computer readable medium for storing pattern size setting program 有权
标题翻译：制造用于存储图案尺寸设定程序的半导体装置和计算机可读介质的方法
公开(公告)号：US08143171B2
公开(公告)日：2012-03-27
申请号：US12403740
申请日：2009-03-13
申请人： Hiromitsu Mashita , Toshiya Kotani , Fumiharu Nakajima , Takafumi Taguchi , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Fumiharu Nakajima , Takafumi Taguchi , Chikaaki Kodama
IPC分类号： H01L21/461
CPC分类号： H01L21/0337
摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.
摘要翻译：通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。

3. 发明申请

US20100241261A1 PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：图案生成方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US20100241261A1
公开(公告)日：2010-09-23
申请号：US12705640
申请日：2010-02-15
申请人： Takafumi TAGUCHI , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
发明人： Takafumi TAGUCHI , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
IPC分类号： G05B13/04 , G06F17/50 , G06F19/00
CPC分类号： G03F1/36
摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.
摘要翻译：基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据执行模式形成模拟。根据模拟结果提取的风险点计算过程条件的最差条件。改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度小于模拟结果。

4. 发明申请

US20090258503A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND COMPUTER READABLE MEDIUM FOR STORING PATTERN SIZE SETTING PROGRAM 有权
标题翻译：用于制造半导体器件的方法和用于存储图案尺寸设置程序的计算机可读介质
公开(公告)号：US20090258503A1
公开(公告)日：2009-10-15
申请号：US12403740
申请日：2009-03-13
申请人： Hiromitsu Mashita , Toshiya Kotani , Fumiharu Nakajima , Takafumi Taguchi , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Fumiharu Nakajima , Takafumi Taguchi , Chikaaki Kodama
IPC分类号： H01L21/306
CPC分类号： H01L21/0337
摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.
摘要翻译：通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。

5. 发明授权

US08617999B2 Method of manufacturing semiconductor device and computer readable medium for storing pattern size setting program 有权
标题翻译：制造用于存储图案尺寸设定程序的半导体装置和计算机可读介质的方法
公开(公告)号：US08617999B2
公开(公告)日：2013-12-31
申请号：US13397750
申请日：2012-02-16
申请人： Hiromitsu Mashita , Toshiya Kotani , Fumiharu Nakajima , Takafumi Taguchi , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Fumiharu Nakajima , Takafumi Taguchi , Chikaaki Kodama
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.
摘要翻译：通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。

6. 发明授权

US08336005B2 Pattern dimension calculation method and computer program product 有权
标题翻译：图案尺寸计算方法和计算机程序产品
公开(公告)号：US08336005B2
公开(公告)日：2012-12-18
申请号：US13050864
申请日：2011-03-17
申请人： Takafumi Taguchi , Toshiya Kotani , Hiromitsu Mashita , Fumiharu Nakajima , Ryota Aburada , Chikaaki Kodama
发明人： Takafumi Taguchi , Toshiya Kotani , Hiromitsu Mashita , Fumiharu Nakajima , Ryota Aburada , Chikaaki Kodama
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.
摘要翻译：根据一个实施例的图案尺寸计算方法计算当在形成在基板上的电路图案的上层中处理电路图案时用作掩模的掩模构件的锥形形状。该方法基于锥形形状从电路图案上的形状预测位置计算面向掩模构件的打开角度。该方法根据在形状预测位置处形成的打开角度来计算电路图案的尺寸。

7. 发明授权

US08266552B2 Pattern generating method, method of manufacturing semiconductor device, and recording medium 有权
标题翻译：图案生成方法，制造半导体器件的方法和记录介质
公开(公告)号：US08266552B2
公开(公告)日：2012-09-11
申请号：US12705640
申请日：2010-02-15
申请人： Takafumi Taguchi , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
发明人： Takafumi Taguchi , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
IPC分类号： G06F17/50 , G06F19/00 , G05B13/04
CPC分类号： G03F1/36
摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.
摘要翻译：基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据来执行模式形成模拟。根据模拟结果提取的风险点计算过程条件的最差条件。改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度小于模拟结果。

8. 发明申请

US20110065030A1 MASK PATTERN DETERMINING METHOD, MASK MANUFACTURING METHOD, AND DEVICE MANUFACTURING METHOD 审中-公开
标题翻译：掩模图形测定方法，掩模制造方法及装置制造方法
公开(公告)号：US20110065030A1
公开(公告)日：2011-03-17
申请号：US12880507
申请日：2010-09-13
申请人： Toshiya KOTANI , Fumiharu Nakajima , Ryota Aburada , Takafumi Taguchi , Hiromitsu Mashita , Michiya Takimoto , Chikaaki Kodama
发明人： Toshiya KOTANI , Fumiharu Nakajima , Ryota Aburada , Takafumi Taguchi , Hiromitsu Mashita , Michiya Takimoto , Chikaaki Kodama
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G06F17/5009 , G03F1/68 , G03F7/70425
摘要： According to one embodiment, a mask pattern determining method includes a mask-pattern dimension variation amount of a first photomask is derived. Moreover, a correspondence relationship between a target dimension value of an on-substrate test pattern formed by using a second photomask and a dimension allowable variation amount of a mask pattern formed on the second photomask is derived. Then, it is determined whether pattern formation is possible with a pattern dimension that needs to be formed when performing the pattern formation on a substrate by using the first photomask based on the mask-pattern dimension variation amount and the correspondence relationship.
摘要翻译：根据一个实施例，掩模图案确定方法包括导出第一光掩模的掩模图案尺寸变化量。此外，导出通过使用第二光掩模形成的基板上测试图案的目标尺寸值与形成在第二光掩模上的掩模图案的尺寸允许变化量之间的对应关系。然后，基于掩模图案尺寸变化量和对应关系，通过使用第一光掩模在基板上进行图案形成时，确定是否可以形成图案尺寸。

9. 发明授权

US08347241B2 Pattern generation method, computer-readable recording medium, and semiconductor device manufacturing method 有权
标题翻译：图案生成方法，计算机可读记录介质和半导体器件制造方法
公开(公告)号：US08347241B2
公开(公告)日：2013-01-01
申请号：US12354119
申请日：2009-01-15
申请人： Fumiharu Nakajima , Toshiya Kotani , Hiromitsu Mashita , Chikaaki Kodama
发明人： Fumiharu Nakajima , Toshiya Kotani , Hiromitsu Mashita , Chikaaki Kodama
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled.
摘要翻译：图案生成方法包括：通过第一处理获取要在过程目标胶片上形成的第一图案的第一设计约束，所述第一设计约束使用作为所述第一图案中的任意一个的图案宽度的索引，以及任意图案之间的空间和与任意图案相邻的图案; 根据第二处理的图案转换来校正第一设计约束，从而获得第二图案的第二设计约束，该第二图案使用在第二图案的预定图案空间的两侧上的两个图案作为索引; 判断设计模式是否符合第二设计约束; 并且当不满足设计约束时，改变设计模式以对应于由第二设计约束允许的值。

10. 发明申请

US20100081265A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100081265A1
公开(公告)日：2010-04-01
申请号：US12557111
申请日：2009-09-10
申请人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
发明人： Hiromitsu Mashita , Toshiya Kotani , Hidefumi Mukai , Fumiharu Nakajima , Chikaaki Kodama
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/0337 , H01L21/32139
摘要： According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
摘要翻译：根据本发明的一个方面，提供一种制造半导体器件的方法，所述方法包括：在靶膜上形成第一膜; 在第一膜上形成抗蚀剂图案; 用抗蚀剂图案处理第一膜以形成第一图案，包括：周期图案; 和非周期性模式; 去除抗蚀剂图案; 在目标膜上形成第二膜; 处理所述第二膜以在所述第一图案的侧壁上形成第二侧壁图案; 去除周期性模式; 用非周期图案和第二侧壁图案处理目标薄膜，从而形成包括周期性目标图案的目标图案; 非周期目标模式; 以及布置在周期性目标图案和非周期性图案之间的虚拟图案，并且周期性地布置有周期性目标图案。

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