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    • 10. 发明授权
    • Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof
    • 用于设计半导体集成电路的布局的方法,通过相同的方法获得的半导体集成电路以及用于验证其定时的方法
    • US06301692B1
    • 2001-10-09
    • US09153063
    • 1998-09-15
    • Shinichi KumashiroHiroshi MizunoYasuhiro TanakaToshiyuki MoriwakiYouichirou Mae
    • Shinichi KumashiroHiroshi MizunoYasuhiro TanakaToshiyuki MoriwakiYouichirou Mae
    • G06F1750
    • G06F17/5022G06F17/5068H01L27/11807
    • First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
    • 首先,将给定逻辑电路分为组合电路部分和寄存器部分。 通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。 每个部分电路被转换成具有晶体管电平的电路。 然后,产生具有晶体管电平的部分电路的布局单元。 此后,通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线,从而创建块布局。 因此,具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。 特别地,具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。 因此,可以获得最佳的驱动能力,并且可以产生具有稳定特性的布局。 另外,可以确保面积减少,低功耗,高速运转等优点。