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    • 2. 发明授权
    • Data processing processor
    • 数据处理处理器
    • US06944696B2
    • 2005-09-13
    • US10673851
    • 2003-09-30
    • Hiroshi YamadaToyokazu HoriMasaru HaseTetsuya YamatoNorihiko Sugita
    • Hiroshi YamadaToyokazu HoriMasaru HaseTetsuya YamatoNorihiko Sugita
    • G06F12/00G06F13/18G06F13/362G06F13/36
    • G06F13/3625
    • A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.
    • 用于图像处理处理器的总线仲裁装置是可操作的,使得当具有高实时处理操作的必要性的信道发布总线使用请求时,总线使用许可不被给予具有低真实性的另一信道 时间处理操作。 数据的总线仲裁器包括:相对于具有高实时处理操作的必要性的信道的下降使用许可时间的计时器,以及用于实时处理操作的必要性低的信道的寄存器。 大于定时器最大值的值被设置为寄存器的值。 在总线仲裁中,将寄存器的值与定时器的值进行比较,然后将总线使用许可赋予具有较小值的通道。
    • 3. 发明授权
    • Data processing processor
    • 数据处理处理器
    • US06658511B2
    • 2003-12-02
    • US09745928
    • 2000-12-26
    • Hiroshi YamadaToyokazu HoriMasaru HaseTetsuya YamatoNorihiko Sugita
    • Hiroshi YamadaToyokazu HoriMasaru HaseTetsuya YamatoNorihiko Sugita
    • G06F1300
    • G06F13/3625
    • A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.
    • 用于图像处理处理器的总线仲裁装置是可操作的,使得当具有高实时处理操作的必要性的信道发布总线使用请求时,总线使用许可不被给予具有低真实性的另一信道 时间处理操作。 数据的总线仲裁器包括:相对于具有高实时处理操作的必要性的信道的下降使用许可时间的计时器,以及用于实时处理操作的必要性低的信道的寄存器。 大于定时器最大值的值被设置为寄存器的值。 在总线仲裁中,将寄存器的值与定时器的值进行比较,然后将总线使用许可赋予具有较小值的通道。
    • 7. 发明授权
    • Discrete cosine transformation operation circuit
    • 离散余弦变换运算电路
    • US06185595B2
    • 2001-02-06
    • US08952653
    • 1998-03-10
    • Toyokazu HoriNario SumiMasaru Hase
    • Toyokazu HoriNario SumiMasaru Hase
    • G06F1714
    • G06F17/147
    • One multiplier 13 operated at a normalized frequency 4 is provided to multiply the elements of DCT transformation coefficients and the elements of input data, and the multiplication results are added by a cumulative adder 15 to determine cumulative addition results corresponding to the sum (x0+x7) and the difference (x0−x7) of a pair of elements (x0, x7) of data to be outputted from a one-dimensional DCT operation circuit 1. The paired cumulative addition results are added and subtracted by an adder 17 and a subtracter 18, respectively, to determine the elements (x0, x7). The operations are performed specific times the number of which is one half of the number of elements of a column of the matrix of the input data to determine the elements of a column of the matrix of the output data and are performed specific times the number of which is equal to the number of elements of a row of the matrix or the input data to determine all the elements of the matrix of the output data. As a result, the scale of the DCT operation circuit is reduced, thereby reducing the power consumption.
    • 提供以归一化频率4操作的一个乘法器13,用于将DCT变换系数的元素和输入数据的元素相乘,乘法结果由累积加法器15相加,以确定对应于和(x0 + x7)的累积加法结果 )和要从一维DCT运算电路1输出的数据的一对元素(x0,x7)的差(x0-x7)。成对的累积相加结果被加法器17和减法器 18,分别确定元素(x0,x7)。 执行操作的特定次数,其数量是输入数据的矩阵的列的元素数量的一半,以确定输出数据的矩阵的列的元素,并且被执行特定次数 其等于矩阵的行的元素的数量或输入数据,以确定输出数据的矩阵的所有元素。 结果,降低了DCT运算电路的规模,从而降低了功耗。
    • 9. 发明授权
    • Motion compensation image coding device and coding method
    • 运动补偿图像编码装置及编码方法
    • US07876829B2
    • 2011-01-25
    • US11286427
    • 2005-11-25
    • Shohei SaitoMasaru HaseFumitaka IzuharaSeiji Mochizuki
    • Shohei SaitoMasaru HaseFumitaka IzuharaSeiji Mochizuki
    • H04N7/12
    • H04N19/523H04N5/145H04N19/57
    • The present invention provides a technology that is implemented in a motion compensation image coding device or a coding method and intended to code motion picture data in real time by performing a decreased number of arithmetic operations so as to determine a motion vector. In motion compensation image coding, macroblocks and sub-blocks into which each of the macroblocks is divided are searched for a motion vector with integer pixel precision. Based on the results of the search, a shape of a block that should be searched for a motion vector with decimal pixel precision is determined as a shape mode. The block of the shape mode is searched for a motion vector with decimal pixel precision, whereby a motion vector needed to produce predictive image data is determined.
    • 本发明提供一种在运动补偿图像编码装置或编码方法中实现的,旨在通过执行减少数量的算术运算来实时编码运动图像数据以确定运动矢量的技术。 在运动补偿图像编码中,对每个宏块分割的宏块和子块搜索具有整数像素精度的运动矢量。 基于搜索结果,确定应该搜索具有小数像素精度的运动矢量的块的形状作为形状模式。 搜索具有十进制像素精度的运动矢量的形状模式的块,由此确定产生预测图像数据所需的运动矢量。