专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140104916A1 SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS 审中-公开
标题翻译：具有存储单元阵列的半导体器件分为多个存储器
公开(公告)号：US20140104916A1
公开(公告)日：2014-04-17
申请号：US14105280
申请日：2013-12-13
申请人： Hiromasa NODA , Yasuji KOSHIKAWA
发明人： Hiromasa NODA , Yasuji KOSHIKAWA
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C8/10 , G11C11/4097
摘要： A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.
摘要翻译：半导体器件包括沿X方向布置的多个存储器垫，以及基于行地址激活存储器垫的一部分并且保持其余的存储器衬垫不被激活的衬垫选择电路。存储器垫被分成多个存储器垫组，每个存储器垫组包括沿X方向布置的相同数量的存储器垫。垫选择电路激活包括在每个存储器垫组中的至少一个存储器垫，同时保持其余的存储器垫不被激活。通过这种操作，在X方向上排列的存储垫中不会发生一部分不连续性，因此消除了在不连续部分中布置两个子字驱动器区域的必要性。

2. 发明申请

US20110026290A1 SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS 审中-公开
标题翻译：具有存储单元阵列的半导体器件分为多个存储器
公开(公告)号：US20110026290A1
公开(公告)日：2011-02-03
申请号：US12848443
申请日：2010-08-02
申请人： Hiromasa NODA , Yasuji KOSHIKAWA
发明人： Hiromasa NODA , Yasuji KOSHIKAWA
IPC分类号： G11C5/02 , G11C7/06
CPC分类号： G11C5/02 , G11C5/025 , G11C8/10 , G11C11/4097
摘要： A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.
摘要翻译：半导体器件包括沿X方向布置的多个存储器垫，以及基于行地址激活存储器垫的一部分并且保持其余的存储器衬垫不被激活的衬垫选择电路。存储器垫被分成多个存储器垫组，每个存储器垫组包括沿X方向布置的相同数量的存储器垫。垫选择电路激活包括在每个存储器垫组中的至少一个存储器垫，同时保持其余的存储器垫不被激活。通过这种操作，在X方向上排列的存储垫中不会发生一部分不连续性，因此消除了在不连续部分中布置两个子字驱动器区域的必要性。

3. 发明申请

US20120075904A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120075904A1
公开(公告)日：2012-03-29
申请号：US13311344
申请日：2011-12-05
申请人： Yasuhiro MATSUMOTO , Yasuji KOSHIKAWA
发明人： Yasuhiro MATSUMOTO , Yasuji KOSHIKAWA
IPC分类号： G11C5/06
CPC分类号： H01L27/0207 , H01L21/26586 , H01L21/823412 , H01L27/088 , H01L27/10894 , H01L27/10897
摘要： A semiconductor device includes a memory cell, a bit line coupled to the memory cell, first and second wells arranged adjacently to each other, the first and second wells being different in conductivity type from each other and defining a boundary therebetween, first and second transistors formed in the first and second wells, respectively, and being different in channel type from each other, gate electrodes of the first and second transistors being connected in common to the bit line, and a third transistor formed in the first well such that the third transistor is sandwiched between the boundary and the first transistor, and a gate of the third transistor being supplied with a bit line precharge signal.
摘要翻译：半导体器件包括存储单元，耦合到存储单元的位线，彼此相邻布置的第一和第二阱，第一和第二阱彼此不同，导电类型彼此不同，并且在其间界定第一和第二晶体管分别形成在第一和第二阱中，并且沟道类型彼此不同，第一和第二晶体管的栅电极共同连接到位线，并且第三晶体管形成在第一阱中，使得第三阱晶体管夹在边界和第一晶体管之间，并且第三晶体管的栅极被提供有位线预充电信号。

4. 发明申请

US20090201757A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090201757A1
公开(公告)日：2009-08-13
申请号：US12426715
申请日：2009-04-20
申请人： Chiaki DONO , Yasuji KOSHIKAWA
发明人： Chiaki DONO , Yasuji KOSHIKAWA
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611
摘要： Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh.
摘要翻译：根据刷新命令的方式（分布式刷新或突发刷新）改变双重刷新执行装置，以便抑制双重刷新时发生的内部电源的下降。

5. 发明申请

US20080089160A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080089160A1
公开(公告)日：2008-04-17
申请号：US11616755
申请日：2006-12-27
申请人： Chiaki DONO , Yasuji KOSHIKAWA , Masayuki NAKAMURA
发明人： Chiaki DONO , Yasuji KOSHIKAWA , Masayuki NAKAMURA
IPC分类号： G11C29/00 , G11C17/18 , G11C7/00
CPC分类号： G11C17/18 , G11C17/165 , G11C29/785 , G11C2229/763
摘要： A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuits 911 is configured to store a first data defining the circuit configuration. A fuse element circuit 913 is configured to store a second data representing inhibition of programming the group of fuse element circuits. A control logic circuit 140 is configured to program the first and the second data on the fuse element circuits. An AND gate circuit 914 is configured to inhibit the control logic circuit 140 from programming the group of fuse element circuits 911 on condition that the fuse element circuit 913 has been programmed.
摘要翻译：半导体器件被配置为防止其中熔丝电路的错误编程。半导体器件包括以下元件。一组熔丝元件电路911被配置为存储限定电路配置的第一数据。熔丝元件电路913被配置为存储表示对熔丝元件电路组编程的禁止的第二数据。控制逻辑电路140被配置为对熔丝元件电路上的第一和第二数据进行编程。 AND门电路914被配置为在熔丝元件电路913被编程的条件下禁止控制逻辑电路140对熔丝元件电路组911进行编程。

6. 发明申请

US20100054035A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100054035A1
公开(公告)日：2010-03-04
申请号：US12325026
申请日：2008-11-28
申请人： Chiaki DONO , Yasuji KOSHIKAWA
发明人： Chiaki DONO , Yasuji KOSHIKAWA
IPC分类号： G11C11/4074
CPC分类号： G11C7/1051 , G11C7/1057 , G11C11/404 , G11C11/407 , H01L21/823462 , H01L27/105 , H01L27/10873 , H01L27/10897
摘要： A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array 33, a row decoder 30, and a sense amplifier 32, surrounded by a bold broken line. Thick-film transistors having a threshold voltage lower than the aforementioned transistors are used for input buffers 11 to 13 and an input/output buffer 26, surrounded by a bold line. Thin-film transistors are used for a clock generator 16, a command decoder 17, a mode register 18, a controller 20, a row address buffer and refresh counter 21, a column address buffer and burst counter 22, a data control circuit 23, a latch circuit 24, a DLL 25, and a column decoder 31. (FIG. 1)
摘要翻译：提供了一种半导体存储器件，其以降低的制造成本具有低功耗和改善的输入/输出缓冲器的传送速率。厚膜晶体管用于由粗体虚线包围的存储单元阵列33，行解码器30和读出放大器32。具有低于上述晶体管的阈值电压的厚膜晶体管用于由粗线包围的输入缓冲器11至13和输入/输出缓冲器26。薄膜晶体管用于时钟发生器16，命令解码器17，模式寄存器18，控制器20，行地址缓冲器和刷新计数器21，列地址缓冲器和突发计数器22，数据控制电路23，锁存电路24，DLL 25和列译码器31.（图1）

7. 发明申请

US20080279020A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080279020A1
公开(公告)日：2008-11-13
申请号：US12171081
申请日：2008-07-10
申请人： Sumio OGAWA , Yasuji KOSHIKAWA
发明人： Sumio OGAWA , Yasuji KOSHIKAWA
IPC分类号： G11C29/04 , G11C8/00
CPC分类号： G11C29/808
摘要： In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired.The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
摘要翻译：在设置有用于对缺陷存储单元进行修复的冗余电路的半导体存储器件中，可以有效地修复不均匀分布的存储单元缺陷。半导体存储器件具有多个存储块，并且存储块包括多个段。代替段的缺陷数据的冗余存储块物理地提供给多个存储块中的每一个。冗余存储器块的块地址被共同地逻辑地分配给多个存储器块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式