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    • 1. 发明授权
    • Semiconductor memory device with a clock circuit for reducing power consumption in a standby state
    • 具有用于在待机状态下降低功耗的时钟电路的半导体存储器件
    • US09112488B2
    • 2015-08-18
    • US13303153
    • 2011-11-23
    • Hiroki Murakami
    • Hiroki Murakami
    • G11C7/10G11C7/22G11C5/14H03K19/00G11C16/20G11C16/30
    • H03K19/0016G11C5/147G11C5/148G11C7/1057G11C7/1084G11C7/225G11C16/20G11C16/30G11C2207/2227
    • A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp for receiving the first or the second operation voltage from the power supply portion; and a N-type transistor Tn connected between the transistor Tp and a base potential. The transistors Tp, Tn construct a logic circuit. The power supply portion supplies the first operation voltage to the source of the transistor Tp in the enable state, and supplies the second operation voltage in a standby state. The second operation voltage is set so that voltage amplitude between gate and source of each transistor Tp, Tn is larger than the threshold value of the transistors Tp, Tn.
    • 提供一种包括能够减少在待机状态期间发生的漏电流的逻辑电路的半导体器件。 半导体器件包括用于提供第一操作电压的电源部分或小于第一操作电压的第二操作电压; 用于从电源部分接收第一或第二操作电压的P型低阈值晶体管Tp; 以及连接在晶体管Tp和基极之间的N型晶体管Tn。 晶体管Tp,Tn构成逻辑电路。 电源部在使能状态下将第一工作电压提供给晶体管Tp的源极,将第二工作电压供给到待机状态。 第二操作电压被设置为使得每个晶体管Tp,Tn的栅极和源极之间的电压幅度大于晶体管Tp,Tn的阈值。
    • 5. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120287712A1
    • 2012-11-15
    • US13303153
    • 2011-11-23
    • Hiroki Murakami
    • Hiroki Murakami
    • G11C16/04H03K19/00H03K19/20G11C5/06H03K19/096
    • H03K19/0016G11C5/147G11C5/148G11C7/1057G11C7/1084G11C7/225G11C16/20G11C16/30G11C2207/2227
    • A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp for receiving the first or the second operation voltage from the power supply portion; and a N-type transistor Tn connected between the transistor Tp and a base potential. The transistors Tp, Tn construct a logic circuit. The power supply portion supplies the first operation voltage to the source of the transistor Tp in the enable state, and supplies the second operation voltage in a standby state. The second operation voltage is set so that voltage amplitude between gate and source of each transistor Tp, Tn is larger than the threshold value of the transistors Tp, Tn.
    • 提供一种包括能够减少在待机状态期间发生的漏电流的逻辑电路的半导体器件。 半导体器件包括用于提供第一操作电压的电源部分或小于第一操作电压的第二操作电压; 用于从电源部分接收第一或第二操作电压的P型低阈值晶体管Tp; 以及连接在晶体管Tp和基极之间的N型晶体管Tn。 晶体管Tp,Tn构成逻辑电路。 电源部在使能状态下将第一工作电压提供给晶体管Tp的源极,将第二工作电压供给到待机状态。 第二操作电压被设置为使得每个晶体管Tp,Tn的栅极和源极之间的电压幅度大于晶体管Tp,Tn的阈值。