专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07068584B2 Signal processor 失效
公开(公告)号：US07068584B2
公开(公告)日：2006-06-27
申请号：US10376247
申请日：2003-03-03
申请人： Hiroki Mouri , Hiroyuki Nakahira , Akira Yamamoto
发明人： Hiroki Mouri , Hiroyuki Nakahira , Akira Yamamoto
IPC分类号： G11B7/00
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10296
摘要： The signal processor includes an analog filter, an analog-to-digital (A-D) converter, an adaptive equalization filter, a quality value calculating circuit, and a control circuit. The analog filter removes high-frequency noises of a played-back signal from a recording medium and amplifies a specific frequency band of the played-back signal. The A-D converter converts the played-back signal from the analog filter into a digital signal. The adaptive equalization filter performs waveform equalization of the played-back signal from the A-D converter while adjusting a tap coefficient of the adaptive equalization filter so as to reduce a difference between an output of the adaptive equalization filter and a target value. The quality value calculating circuit calculates a quality value based on the difference between the output of the adaptive equalization filter and the target value. The control circuit compares the quality value calculated by the quality value calculating circuit with a predetermined reference value, and conducts a process for improving the quality value according to the comparison result.

2. 发明授权

US08270269B2 Timing extraction device and video display device 失效
标题翻译：定时提取装置和视频显示装置
公开(公告)号：US08270269B2
公开(公告)日：2012-09-18
申请号：US11918236
申请日：2005-11-11
申请人： Hiroki Mouri , Akira Yamamoto
发明人： Hiroki Mouri , Akira Yamamoto
IPC分类号： G11B5/09
CPC分类号： H04L7/04 , G11B20/10009 , G11B2020/1287
摘要： An asynchronous timing detector 3 detects and measures a specific pattern (sync pattern) of audio and video reproduced signals having a digital value form an A/D converter 2 and its appearance interval based on an asynchronous clock generated by an asynchronous clock generator 4, and calculates a cycle ratio of the measured sync pattern appearance interval (the number of clock pulses of the asynchronous clock) to a normal value (the number of clock pulses of a synchronous clock obtained by measuring a sync pattern appearance interval using the synchronous clock). A pseudo-synchronous clock generator 7 thins the asynchronous clock based on the cycle ratio to generate a pseudo-synchronous clock which is pseudo-synchronous with channel data. Therefore, even when an initial frequency error is large, frequency and phase pull-in is relatively quickly performed until a timing recovery operation becomes stable.
摘要翻译：异步定时检测器3基于由异步时钟发生器4产生的异步时钟来检测并测量具有A / D转换器2的数字值的音频和视频再现信号的特定模式（同步模式）及其出现间隔，以及将所测量的同步图形显示间隔（异步时钟的时钟脉冲数）的周期比计算到正常值（通过使用同步时钟测量同步模式出现间隔而获得的同步时钟的时钟脉冲数）。伪同步时钟发生器7基于该周期比使该异步时钟产生一个与通道数据伪同步的伪同步时钟。因此，即使在初始频率误差大的情况下，相对快速地执行频率和相位拉入，直到定时恢复操作变得稳定。

3. 发明申请

US20090086588A1 Timing extractor, and information playback apparatus and dvd device using the timing extractor 有权
标题翻译：定时提取器，以及使用定时提取器的信息播放装置和DVD设备
公开(公告)号：US20090086588A1
公开(公告)日：2009-04-02
申请号：US11667299
申请日：2006-07-18
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B21/08
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/1403 , G11B2020/1476 , G11B2220/2562 , H03L7/091 , H03L7/1976 , H04L7/02 , H04L7/033
摘要： In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.
摘要翻译：在从再现信号中提取定时信息的前馈定时提取器中，频率比计算部分2通过利用特定的模式和特定的模式来计算重放信号的频率与频率合成器6的输出时钟的频率之间的比率重放信号中的图案出现间隔。控制部分4以频率比计算部分2计算出的频率比具有设定值的方式控制频率合成器6的分频率。因此，与频率合成器6的输出时钟为高频固定速度时钟的情况相比，不需要以高速操作数字电路。因此，即使在信号的重放频率（播放速度）随时间变化的情况下，消除固定时钟的脉冲的抽取率恒定，从而降低功耗。

4. 发明申请

US20090060451A1 Timing Extraction Device and Video Display Device 失效
标题翻译：定时提取设备和视频显示设备
公开(公告)号：US20090060451A1
公开(公告)日：2009-03-05
申请号：US11918236
申请日：2005-11-11
申请人： Hiroki Mouri , Akira Yamamoto
发明人： Hiroki Mouri , Akira Yamamoto
IPC分类号： H04N5/95 , G11B20/10
CPC分类号： H04L7/04 , G11B20/10009 , G11B2020/1287
摘要： An asynchronous timing detector 3 detects and measures a specific pattern (sync pattern) of audio and video reproduced signals having a digital value form an A/D converter 2 and its appearance interval based on an asynchronous clock generated by an asynchronous clock generator 4, and calculates a cycle ratio of the measured sync pattern appearance interval (the number of clock pulses of the asynchronous clock) to a normal value (the number of clock pulses of a synchronous clock obtained by measuring a sync pattern appearance interval using the synchronous clock). A pseudo-synchronous clock generator 7 thins the asynchronous clock based on the cycle ratio to generate a pseudo-synchronous clock which is pseudo-synchronous with channel data. Therefore, even when an initial frequency error is large, frequency and phase pull-in is relatively quickly performed until a timing recovery operation becomes stable.
摘要翻译：异步定时检测器3基于由异步时钟发生器4产生的异步时钟来检测并测量具有A / D转换器2的数字值的音频和视频再现信号的特定模式（同步模式）及其出现间隔，以及将所测量的同步图形显示间隔（异步时钟的时钟脉冲数）的周期比计算到正常值（通过使用同步时钟测量同步模式出现间隔而获得的同步时钟的时钟脉冲数）。伪同步时钟发生器7基于该周期比使该异步时钟产生一个与通道数据伪同步的伪同步时钟。因此，即使在初始频率误差大的情况下，相对快速地执行频率和相位拉入，直到定时恢复操作变得稳定。

5. 发明申请

US20050270677A1 Write compensation circuit and signal interpolation circuit of recording device 有权
公开(公告)号：US20050270677A1
公开(公告)日：2005-12-08
申请号：US11198950
申请日：2005-08-08
申请人： Hirokuni Fujivama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
发明人： Hirokuni Fujivama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B5/00 , G11B5/09 , G11B20/10 , H03K5/08 , H03K5/13
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.

6. 发明授权

US08098972B2 Reproduced signal processor and video display 失效
标题翻译：转载信号处理器和视频显示
公开(公告)号：US08098972B2
公开(公告)日：2012-01-17
申请号：US12526746
申请日：2007-11-01
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
IPC分类号： H04N5/932 , H04N5/935
CPC分类号： H04L7/0331 , G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/14 , G11B2020/1287 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562 , H03L7/06
摘要： In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.
摘要翻译：在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。结果，降低了时钟频率的变化对解码处理的响应的影响。

7. 发明申请

US20110095786A1 PHASE COMPARATOR, PLL CIRCUIT, INFORMATION REPRODUCTION PROCESSING DEVICE, OPTICAL DISK PLAYBACK DEVICE AND MAGNETIC DISK PLAYBACK DEVICE 审中-公开
标题翻译：相位比较器，PLL电路，信息再现处理装置，光盘播放装置和磁盘播放装置
公开(公告)号：US20110095786A1
公开(公告)日：2011-04-28
申请号：US12515337
申请日：2008-09-22
申请人： Akira Yamamoto , Yoshinori Shirakawa , Kouji Okamoto , Hiroki Mouri
发明人： Akira Yamamoto , Yoshinori Shirakawa , Kouji Okamoto , Hiroki Mouri
IPC分类号： H03D13/00
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/10425 , G11B20/14 , G11B2220/2537 , H03L7/091 , H04L7/0334
摘要： In a phase comparator used for a sync clock extraction circuit for extracting a clock synchronizing with reproduction data, a zero cross detection section 701, receiving the reproduction data, outputs a rising cross detection signal, a falling cross detection signal and three phase error candidates that are three consecutive samples. Rising and falling reference value hold sections 703 and 704 respectively output rising and falling reference values. When receiving the rising or falling cross detection signal, a phase error calculation section 702 outputs a sample the difference of which from the rising or falling reference value is minimum in absolute value, out of the three samples including a zero cross sample, as a phase error. The phase error is held in the rising or falling reference value hold section 703 or 704 as the rising or falling reference value for the next phase error calculation.
摘要翻译：在用于提取与再现数据同步的时钟的同步时钟提取电路的相位比较器中，接收再现数据的零交叉检测部分701输出上升交叉检测信号，下降交叉检测信号和三相误差候选，是连续三个样本。上升和下降参考值保持部分703和704分别输出上升和下降参考值。当接收到上升或下降的交叉检测信号时，相位误差计算部分702将包含零交叉样本的三个样本中的从上升或下降基准值的差值的绝对值的差值输出为相位错误。相位误差保持在上升或下降基准值保持部分703或704中作为下一个相位误差计算的上升或下降基准值。

8. 发明授权

US07523154B2 Write compensation circuit and signal interpolation circuit of recording device 有权
标题翻译：写记录装置的补偿电路和信号插补电路
公开(公告)号：US07523154B2
公开(公告)日：2009-04-21
申请号：US11198950
申请日：2005-08-08
申请人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
发明人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
IPC分类号： G06G7/00
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
摘要翻译：记录装置的写补偿电路包括由第一驱动电压驱动的第一延迟部分，用于接收时钟信号，延迟时钟信号第一延迟时间，并输出延迟时钟信号;以及电压提供部分，用于提供第一驱动电压到第一延迟部分，使得第一延迟时间基本上等于时钟信号的时钟周期。

9. 发明授权

US07065029B2 Signal processor 失效
公开(公告)号：US07065029B2
公开(公告)日：2006-06-20
申请号：US10170581
申请日：2002-06-14
申请人： Hiroki Mouri , Kouichi Nagano , Akira Yamamoto
发明人： Hiroki Mouri , Kouichi Nagano , Akira Yamamoto
IPC分类号： G11B7/00
CPC分类号： G11B20/10166 , G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10212
摘要： A waveform equalizer, which has a partial response characteristic represented in the form of PR (a, b, c, b, a) which is a quaternary transfer function characteristic, is made up an analog filter, an ADC (analog/digital converter), and an FIR filter, for providing matching with the frequency characteristic of a read back waveform read from a recording medium. Such signal processor characteristic approximation to the regenerative signal characteristic makes it possible to easily achieve equalization without particularly emphasizing the regenerative signal, thereby achieving a reduced circuit scale.

10. 发明授权

US06970313B1 Write compensation circuit and signal interpolation circuit of recording device 失效
标题翻译：写记录装置的补偿电路和信号插补电路
公开(公告)号：US06970313B1
公开(公告)日：2005-11-29
申请号：US09539206
申请日：2000-03-30
申请人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
发明人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B5/00 , G11B5/09 , G11B20/10 , H03K5/08 , H03K5/13
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
摘要翻译：记录装置的写补偿电路包括由第一驱动电压驱动的第一延迟部分，用于接收时钟信号，延迟时钟信号第一延迟时间，并输出延迟时钟信号;以及电压提供部分，用于提供第一驱动电压到第一延迟部分，使得第一延迟时间基本上等于时钟信号的时钟周期。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式