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    • 3. 发明授权
    • Sample-and-hold circuit including a robust leakage current compensating
circuit
    • 采样保持电路包括鲁棒的漏电流补偿电路
    • US5691657A
    • 1997-11-25
    • US600007
    • 1996-02-14
    • Yoji HiranoGoro Ueda
    • Yoji HiranoGoro Ueda
    • G11C27/02H03F3/04H03M1/12
    • G11C27/026
    • A sample-and-hold circuit comprises an analog signal control circuit for supplying a potential of an input signal to one end of a hold capacitor, a first transistor having a base connected to the one end of the hold capacitor and operating in an emitter follower fashion, an amplifier having a second transistor having a base connected to an emitter of the first transistor, and a leak current compensating circuit including a third transistor having an emitter connected to a collector of the first transistor and a current mirror circuit for supplying to the base of the first transistor the same current as a base current of the third transistor.
    • 采样保持电路包括用于向保持电容器的一端提供输入信号的电位的模拟信号控制电路,第一晶体管,其基极连接到保持电容器的一端,并在发射极跟随器 具有第二晶体管的放大器,其具有连接到第一晶体管的发射极的基极,以及漏电流补偿电路,包括具有连接到第一晶体管的集电极的发射极的第三晶体管和用于向第一晶体管供电的电流镜电路 第一晶体管的基极与第三晶体管的基极电流相同的电流。
    • 4. 发明授权
    • Current buffer circuit with enhanced response speed to input signal
    • 电流缓冲电路,对输入信号的响应速度提高
    • US5550501A
    • 1996-08-27
    • US392257
    • 1995-02-22
    • Masahiro ItoYoji Hirano
    • Masahiro ItoYoji Hirano
    • H03K17/66H03F3/30H03K19/013H03K17/04
    • H03F3/3076H03K19/0136
    • A current buffer circuit comprises an input terminal, an output terminal, a first transistor of a first conductivity type having a base connected to the input terminal and an emitter, and a second transistor of a second conductivity type having a base connected to the input terminal and an emitter. The buffer circuit further includes a third transistor of the second conductivity type having a base connected to the emitter of the first transistor, a collector connected to a first power supply terminal, and an emitter connected to the output terminal, a fourth transistor of the first conductivity type having a base connected to the emitter of the second transistor, a collector connected to a second power supply terminal, and an emitter connected to the output terminal, and a fifth transistor of the second conductivity type having a base connected to the collector of said fourth transistor, a collector connected to said output terminal, and an emitter connected to the second power supply terminal. The fifth transistor becomes conductive when the current flows from the output terminal to the second power supply terminal through the fourth transistor.
    • 电流缓冲电路包括输入端子,输出端子,具有连接到输入端子的基极的第一导电类型的第一晶体管和发射极,以及具有连接到输入端子的基极的第二导电类型的第二晶体管 和发射器。 缓冲电路还包括第二导电类型的第三晶体管,其具有连接到第一晶体管的发射极的基极,连接到第一电源端子的集电极和连接到输出端子的发射极,第一晶体管的第四晶体管 具有连接到第二晶体管的发射极的基极的导电类型,连接到第二电源端子的集电极和连接到输出端子的发射极,以及第二导电类型的第五晶体管, 所述第四晶体管,连接到所述输出端子的集电极和连接到所述第二电源端子的发射极。 当电流从第四晶体管从输出端流向第二电源端时,第五晶体管导通。
    • 5. 发明授权
    • Variable gain amplifier circuit with reduced power requirements
    • 具有降低功耗要求的可变增益放大器电路
    • US5818300A
    • 1998-10-06
    • US788443
    • 1997-01-28
    • Yoji Hirano
    • Yoji Hirano
    • H03G3/10H03F3/45H03G1/00H03H11/46
    • H03F3/45085H03F3/45089H03G1/0023H03F2203/45352H03F2203/45392H03F2203/45701
    • In a differential amplifier formed with first and second transistors having emitters connected to each other via a resistor, an input signal is supplied to a base of the first transistor. On the other hand, to a base of the second transistor, an external constant voltage is supplied. In order to control the emitter current of the second transistor, a third transistor having a base supplied a control voltage is added. The emitter of the third transistor is commonly connected to the emitter of the second transistor in common, and a collector thereof is connected to a high power source voltage terminal. By varying at least one of the control voltage on the base of the third transistor and the constant voltage on the base of the second transistor, a gain of the circuit can be controlled. Also, the transistors are connected in single stage connection with respect to the power source, operation with the low power source voltage becomes possible.
    • 在由具有经由电阻器彼此连接的发射极的第一和第二晶体管形成的差分放大器中,输入信号被提供给第一晶体管的基极。 另一方面,向第二晶体管的基极提供外部恒定电压。 为了控制第二晶体管的发射极电流,增加具有提供控制电压的基极的第三晶体管。 第三晶体管的发射极共同地连接到第二晶体管的发射极,其集电极连接到高电源电压端子。 通过改变第三晶体管的基极上的控制电压和第二晶体管的基极上的恒定电压中的至少一个,可以控制电路的增益。 此外,晶体管相对于电源连接在单级连接中,具有低电源电压的操作成为可能。
    • 8. 发明授权
    • Aluminum alloy brazing material and brazing sheet adaptable for heat
exchanges
    • 铝合金钎焊材料和钎焊板适用于热交换
    • US5744255A
    • 1998-04-28
    • US707091
    • 1996-09-03
    • Takeyoshi DokoKoji OkadaTokinori OndaHiroaki TakeuchiYoji Hirano
    • Takeyoshi DokoKoji OkadaTokinori OndaHiroaki TakeuchiYoji Hirano
    • B23K35/02B23K35/28B32B15/01F28F21/08B32B15/20F28F19/06
    • F28F21/089B23K35/286B32B15/016F28F21/084B23K35/0238B23K35/288Y10S165/905Y10S428/933Y10T428/12764
    • A typical aluminum alloy brazing material includesover 7.0 wt. % and not more than 12.0 wt. % of Si: over 0.1 wt. % and not more than 8.0 wt. % of Cu. over 0.05 wt. % and not more than 0.5 wt. % or Fe, further at least one kind selected from a group consisting of over 0.5 wt. % and not more than 5.5 wt. % of Zn. over 0.002 wt. % and not more than 0.3 wt % of In and over 0.002 wt. % and not more than 0.3 wt. % of Sn, and the balance of Al an inevitable impurities. A typical cladded aluminum alloy brazing sheet with a three-layer structure includes a brazing material, a core material comprising over 0.6 wt. % and not more than 2.5 wt. % of Si, over 0.5 wt. % and not more 2.5 wt. % of Cu, over 0.05 wt. % and not more than 2.0 wt. % of Mn, and the balance of Al and inevitable impurities, and a sacrificial material comprising at least one kind selected from a group consisting of over 0.5 wt. % and not more than 6.0 wt. % of Zn. over 0.002 wt. % and not more than 0.3 wt. % of In, and over 0.002 wt. % and not more than 0.3 wt. % of Sn, and the balance of Al and inevitable impurities, or comprises a core material cladded both sides thereof with the brazing material. By using the inventive brazing materials or brazing sheets, the brazing heating can be performed at a temperature of 570.degree. to 585.degree. C.
    • 典型的铝合金钎料包括7.0重量% %且不超过12.0wt。 Si%:超过0.1wt。 %且不大于8.0wt。 %的铜。 超过0.05重量% %且不大于0.5wt。 %或Fe,还有至少一种选自超过0.5wt。 %且不超过5.5重量% %的Zn。 超过0.002重量% %且不超过0.3重量%的In和0.002重量% %且不超过0.3wt。 %的Sn,其余的Al是不可避免的杂质。 具有三层结构的典型的包覆铝合金钎焊板包括钎焊材料,芯材料包含超过0.6重量% %且不大于2.5wt。 %的Si,超过0.5wt。 %而不多2.5重量% %的Cu,超过0.05wt。 %且不超过2.0wt。 Mn的百分比,Al和不可避免的杂质的余量,以及包含选自由0.5重量%以上的至少一种的牺牲材料。 %且不超过6.0重量% %的Zn。 超过0.002重量% %且不超过0.3wt。 的In,以及0.002重量%以上。 %且不超过0.3wt。 的Sn,余量由Al和不可避免的杂质构成,或者是由钎焊材料的两面包覆的芯材构成。 通过使用本发明的钎焊材料或钎焊片,钎焊加热可以在570℃至585℃的温度下进行。