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1. 发明申请

US20120007189A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US20120007189A1
公开(公告)日：2012-01-12
申请号：US13240901
申请日：2011-09-22
申请人： HIROHARU SHIMIZU , Masakazu Nishibori , Toshihiko Ochiai
发明人： HIROHARU SHIMIZU , Masakazu Nishibori , Toshihiko Ochiai
IPC分类号： H01L27/092
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/11807
摘要： To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells.In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
摘要翻译：提供即使在高度小型化的电路单元中也可以防止电路可靠性劣化的电路布局设计方法。为了防止来自电源电位的噪声或具有大电位差的参考电位影响栅电极并引起故障，连接到栅电极的第一插头和电源电位或参考电压的第二插头需要提供的电位彼此间隔足以使来自电源电位的噪声或参考电位不影响第一插头的距离。为此，在平面布置设计时，在布线等间隔放置的第二插头中，只有放置在与第一插头不足够间隔的布置位置的第二插头被删除。

2. 发明申请

US20100059794A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US20100059794A1
公开(公告)日：2010-03-11
申请号：US12545843
申请日：2009-08-23
申请人： Hiroharu SHIMIZU , Masakazu Nishibori , Toshihiko Ochiai
发明人： Hiroharu SHIMIZU , Masakazu Nishibori , Toshihiko Ochiai
IPC分类号： H01L27/092 , G06F17/50
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/11807
摘要： To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells.In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
摘要翻译：提供即使在高度小型化的电路单元中也可以防止电路可靠性劣化的电路布局设计方法。为了防止来自电源电位的噪声或具有大电位差的参考电位影响栅电极并引起故障，连接到栅电极的第一插头和电源电位或参考电压的第二插头需要提供的电位彼此间隔足以使来自电源电位的噪声或参考电位不影响第一插头的距离。为此，在平面布置设计时，在布线等间隔放置的第二插头中，只有放置在与第一插头不足够间隔的布置位置的第二插头被删除。

3. 发明授权

US08354697B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
公开(公告)号：US08354697B2
公开(公告)日：2013-01-15
申请号：US13240901
申请日：2011-09-22
申请人： Hiroharu Shimizu , Masakazu Nishibori , Toshihiko Ochiai
发明人： Hiroharu Shimizu , Masakazu Nishibori , Toshihiko Ochiai
IPC分类号： H01L27/10
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/11807
摘要： To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells.In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.

4. 发明授权

US08043900B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08043900B2
公开(公告)日：2011-10-25
申请号：US12545843
申请日：2009-08-23
申请人： Hiroharu Shimizu , Masakazu Nishibori , Toshihiko Ochiai
发明人： Hiroharu Shimizu , Masakazu Nishibori , Toshihiko Ochiai
IPC分类号： H01L21/82
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/11807
摘要： To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells.In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
摘要翻译：提供即使在高度小型化的电路单元中也可以防止电路可靠性劣化的电路布局设计方法。为了防止来自电源电位的噪声或具有大电位差的参考电位影响栅电极并引起故障，连接到栅电极的第一插头和电源电位或参考电压的第二插头需要提供的电位彼此间隔足以使来自电源电位的噪声或参考电位不影响第一插头的距离。为此，在平面布置设计时，在布线等间隔放置的第二插头中，只有放置在与第一插头不足够间隔的布置位置的第二插头被删除。

5. 发明申请

US20060273837A1 Pulse latch circuit and semiconductor integrated circuit 失效
标题翻译：脉冲锁存电路和半导体集成电路
公开(公告)号：US20060273837A1
公开(公告)日：2006-12-07
申请号：US11442273
申请日：2006-05-30
申请人： Yasuhisa Shimazaki , Masakazu Nishibori
发明人： Yasuhisa Shimazaki , Masakazu Nishibori
IPC分类号： H03K3/289
CPC分类号： G01R31/318575 , H03K3/012 , H03K3/356156
摘要： The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.
摘要翻译：所公开的发明旨在降低脉冲锁存电路的功耗。包括执行移位测试图形扫描数据的第一操作模式和未执行移动测试图形扫描数据的第二操作模式的脉冲锁存电路与脉冲时钟信号同步操作，包括以下电路：能够与时钟信号同步地锁存输入数据的第一锁存电路; 第二锁存电路，连接到第一锁存电路并且能够锁存与时钟信号同步地移位的测试图形扫描数据; 以及控制电路，其在第二操作模式期间停止向第二锁存电路提供时钟信号。通过这样停止向第二锁存电路提供时钟信号，实现了功耗的降低。

6. 发明授权

US07768294B2 Pulse latch circuit and semiconductor integrated circuit 失效
标题翻译：脉冲锁存电路和半导体集成电路
公开(公告)号：US07768294B2
公开(公告)日：2010-08-03
申请号：US12171957
申请日：2008-07-11
申请人： Yasuhisa Shimazaki , Masakazu Nishibori
发明人： Yasuhisa Shimazaki , Masakazu Nishibori
IPC分类号： H03K19/00
CPC分类号： G01R31/318575 , H03K3/012 , H03K3/356156
摘要： The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.
摘要翻译：所公开的发明旨在降低脉冲锁存电路的功耗。包括执行移位测试图形扫描数据的第一操作模式和未执行移动测试图形扫描数据的第二操作模式的脉冲锁存电路与脉冲时钟信号同步操作，包括以下电路：能够与时钟信号同步地锁存输入数据的第一锁存电路; 第二锁存电路，连接到第一锁存电路并且能够锁存与时钟信号同步地移位的测试图形扫描数据; 以及控制电路，其在第二操作模式期间停止向第二锁存电路提供时钟信号。通过这样停止向第二锁存电路提供时钟信号，实现了功耗的降低。

7. 发明授权

US07411413B2 Pulse latch circuit and semiconductor integrated circuit 失效
标题翻译：脉冲锁存电路和半导体集成电路
公开(公告)号：US07411413B2
公开(公告)日：2008-08-12
申请号：US11442273
申请日：2006-05-30
申请人： Yasuhisa Shimazaki , Masakazu Nishibori
发明人： Yasuhisa Shimazaki , Masakazu Nishibori
IPC分类号： H03K19/00 , H03K3/00
CPC分类号： G01R31/318575 , H03K3/012 , H03K3/356156
摘要： The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.
摘要翻译：所公开的发明旨在降低脉冲锁存电路的功耗。包括执行移位测试图形扫描数据的第一操作模式和未执行移动测试图形扫描数据的第二操作模式的脉冲锁存电路与脉冲时钟信号同步操作，包括以下电路：能够与时钟信号同步地锁存输入数据的第一锁存电路; 第二锁存电路，连接到第一锁存电路并且能够锁存与时钟信号同步地移位的测试图形扫描数据; 以及控制电路，其在第二操作模式期间停止向第二锁存电路提供时钟信号。通过这样停止向第二锁存电路提供时钟信号，实现了功耗的降低。

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