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1. 发明授权

US06369409B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06369409B1
公开(公告)日：2002-04-09
申请号：US08689867
申请日：1996-08-15
申请人： Hiroaki Takasu , Jun Osanai , Kenji Kitamura
发明人： Hiroaki Takasu , Jun Osanai , Kenji Kitamura
IPC分类号： F02K900
CPC分类号： H01L28/20 , H01L21/8221 , H01L21/84 , H01L27/0802 , H01L27/1203
摘要： It is an object to provide a highly precise bleeder resistance circuit having an accurate voltage division ratio and a small temperature coefficient of the resistance value and a highly precise semiconductor device having a small temperature coefficient using such a bleeder resistance circuit, e.g., a semiconductor device such as a voltage detector and a voltage regulator. Such characteristic features that the potential of electric conductors on the thin film resistors and electric conductors under the thin film resistors of a bleeder resistance circuit using thin film resistors is made almost equal to the potential of respective thin film resistors and that, when polysilicon is used in the thin film resistor, the dispersion of the resistance value is controlled and the temperature dependency of the resistance value is made lower by thinning the film thickness of the polysilicon thin film resistor are constituted.
摘要翻译：本发明的目的是提供具有精确的分压比和较小的电阻值温度系数的高精度放电电阻电路，以及使用这种泄放电阻电路（例如半导体器件）具有较小温度系数的高精度半导体器件例如电压检测器和电压调节器。使用薄膜电阻器的泄放电阻电路的薄膜电阻器和薄膜电阻器下方的电导体的电位与各薄膜电阻器的电位几乎相等的特征在于，当使用多晶硅时在薄膜电阻器中，控制电阻值的分散，并且通过使多晶硅薄膜电阻器的膜厚变薄来降低电阻值的温度依赖性。

2. 发明授权

US08450799B2 Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权
公开(公告)号：US08450799B2
公开(公告)日：2013-05-28
申请号：US11975923
申请日：2007-10-22
申请人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
IPC分类号： H01L29/34
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.

3. 发明授权

US07282763B2 Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权
标题翻译：形成在绝缘基板上的场效应晶体管及其集成电路
公开(公告)号：US07282763B2
公开(公告)日：2007-10-16
申请号：US10228847
申请日：2002-08-27
申请人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
IPC分类号： H01L29/94
CPC分类号： H01L29/78615 , H01L29/42384 , H01L29/78645
摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film formed on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor thin film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. A conductive thin film is connected with the second region and the third region. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation and without application of a fixed bias potential to the third region.
摘要翻译：场效应晶体管具有绝缘基板，形成在绝缘基板上的半导体薄膜和形成在半导体薄膜上的栅极绝缘膜。在栅极绝缘膜上形成第一栅电极。在第一栅电极的长度方向的相对侧的半导体薄膜的表面上或表面上形成具有第一导电类型的第一区域和第二区域。具有与第一导电类型相反的第二导电类型的第三区域与第一栅电极的宽度方向上的第二区域并排设置在半导体膜上或半导体膜中。导电薄膜与第二区域和第三区域连接。第二栅电极沿着第二区形成在栅极绝缘膜上。具有第一导电类型的第四区域形成在第二区域的相对于第二栅电极的相反侧上或半导体膜中。根据电路操作将第一和第四区域中的一个用作输出区域，并且不向第三区域施加固定的偏置电位。

4. 发明授权

US06653688B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06653688B2
公开(公告)日：2003-11-25
申请号：US10116666
申请日：2002-04-03
申请人： Hiroaki Takasu , Jun Osanai
发明人： Hiroaki Takasu , Jun Osanai
IPC分类号： H01L2362
CPC分类号： H01L28/20 , H01L27/016
摘要： A semiconductor device comprises a MOS transistor and a resistor. The resistor has a P-type resistor formed from a P-type semiconductor, an N-type resistor formed from an N-type semiconductor and disposed adjacent the P-type resistor, and an insulating film disposed between the P-type and N-type resistors. The P-type resistor is arranged at the low potential side of the semiconductor device and the N-type resistor is arranged at the high potential side thereof. A portion of the insulating film between the P-type and N-type resistors is made electrically conductive by irradiating the portion with a laser beam to destroy the insulating property thereof to thereby achieve conductivity between the P-type and N-type resistors. A gate electrode of the MOS transistor is formed of a P-type polysilicon thin film having the same high concentration impurity as that of the region where the P-type resistor is in contact with a metal wiring, thereby enhancing the current driving capacity of a driver MOS.
摘要翻译：半导体器件包括MOS晶体管和电阻器。电阻器具有由P型半导体形成的P型电阻器，由N型半导体形成并配置在P型电阻器附近的N型电阻器，以及设置在P型和N型半导体器件之间的绝缘膜，型电阻。 P型电阻器配置在半导体器件的低电位侧，N型电阻器配置在高电位侧。 P型和N型电阻之间的绝缘膜的一部分通过用激光束照射该部分而导电，从而破坏其绝缘性能，从而实现P型和N型电阻之间的导电性。 MOS晶体管的栅电极由与P型电阻器与金属布线接触的区域具有相同的高浓度杂质的P型多晶硅薄膜形成，从而提高了电流驱动能力驱动器MOS。

5. 发明授权

US06492236B2 Method of manufacturing a semiconductor device with a silicide 失效
标题翻译：制造具有硅化物的半导体器件的方法
公开(公告)号：US06492236B2
公开(公告)日：2002-12-10
申请号：US10096394
申请日：2002-03-12
申请人： Hiroaki Takasu , Jun Osanai
发明人： Hiroaki Takasu , Jun Osanai
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/7833
摘要： There is provided a manufacturing method for obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance. A source and a drain, which have a low concentration, are formed and a thick insulating film and positive resist is formed (applied) on a gate electrode. Then, the positive resist is exposed at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developed. The thick insulating film is etched by an amount substantially corresponding to a film thickness thereof by anisotropic etching using as a mask those portions of the positive resist partially remaining in a step portion. An impurity having a high concentration is simultaneously introduced into the source, the drain, and the gate electrode using a remaining portion of the thick insulating film as a mask. After that, high-melting metallic silicide is formed on exposed portions of the gate electrode and the source and drain regions of the MOS transistor, respectively.
摘要翻译：提供一种用于获得具有单极栅极结构和高熔点金属硅化物结构并且甚至适用于高速操作的MOS晶体管的制造方法，同时具有足够的耐受电压的结构通过简单的方法形成具有长距离的低浓度排放区域来实现。形成低浓度的源极和漏极，并且在栅极上形成（施加）厚的绝缘膜和正性抗蚀剂。然后，正极抗蚀剂以适于暴露与形成在厚绝缘膜的平坦部分上的正性抗蚀剂的膜厚度相对应的部分作为基底的曝光量被曝光并显影。通过使用作为掩模的各向异性蚀刻将厚的绝缘膜蚀刻成基本上对应于其膜厚的量，正极抗蚀剂的那些部分部分残留在台阶部分中。使用厚绝缘膜的剩余部分作为掩模，同时将高浓度的杂质引入源极，漏极和栅电极。之后，分别在MOS晶体管的栅极电极和源极和漏极区域的露出部分上形成高熔点金属硅化物。

6. 发明申请

US20090101973A1 Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权
标题翻译：形成在绝缘基板上的场效应晶体管及其集成电路
公开(公告)号：US20090101973A1
公开(公告)日：2009-04-23
申请号：US11975923
申请日：2007-10-22
申请人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
IPC分类号： H01L29/78
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.
摘要翻译：场效应晶体管具有绝缘基板，形成在绝缘基板上的半导体薄膜和半导体薄膜上的栅极绝缘膜。在栅极绝缘膜上形成第一栅电极。在第一栅电极的长度方向的相对侧的半导体膜的表面上或表面上形成具有第一导电类型的第一区域和第二区域。具有与第一导电类型相反的第二导电类型的第三区域与第一栅电极的宽度方向上的第二区域并排设置在半导体膜上或半导体膜中。第三区域和第二区域彼此接触并形成低电阻结。第二栅电极沿着第二区形成在栅极绝缘膜上。具有第一导电类型的第四区域形成在第二区域的相对于第二栅电极的相反侧上或半导体膜中。根据电路操作将第一和第四区域中的一个用作输出区域。

7. 发明授权

US08283725B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08283725B2
公开(公告)日：2012-10-09
申请号：US12191674
申请日：2008-08-14
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L23/62
CPC分类号： H01L29/0646 , H01L21/823418 , H01L27/0266 , H01L29/78
摘要： In a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection surrounded by a shallow trench for device isolation, in order to suppress the off-leak current in an off state, there is formed, in the vicinity of the drain region of the NMOS transistor for ESD protection, an n-type region receiving a signal from an external connection terminal via a p-type region in contact with the drain region of the NMOS transistor for ESD protection.
摘要翻译：在包括由用于器件隔离的浅沟槽围绕的用于静电放电保护的n型金属氧化物半导体晶体管的半导体器件中，为了抑制处于断开状态的漏电流，在漏极附近形成用于ESD保护的NMOS晶体管的区域，n型区域，经由与用于ESD保护的NMOS晶体管的漏极区域接触的p型区域从外部连接端子接收信号。

8. 发明申请

US20120168844A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120168844A1
公开(公告)日：2012-07-05
申请号：US13374281
申请日：2011-12-20
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L29/42324
摘要： Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a tunnel region; the tunnel region and the peripheral of the tunnel region are dug down to be made lower, and a depletion electrode, to which an arbitral potential is given to deplete a part of the tunnel region through a depletion electrode insulating film, is arranged in the lowered drain region.
摘要翻译：提供了具有隧道区域的电可擦除和可编程的非易失性半导体存储器件; 隧道区域和隧道区域的周边被挖掘下来，并且通过耗尽电极绝缘膜将给予仲裁电位以耗尽隧道区域的一部分的耗尽电极布置在下降的漏区。

9. 发明申请

US20090050967A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090050967A1
公开(公告)日：2009-02-26
申请号：US12191674
申请日：2008-08-14
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L29/78
CPC分类号： H01L29/0646 , H01L21/823418 , H01L27/0266 , H01L29/78
摘要： In a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection surrounded by a shallow trench for device isolation, in order to suppress the off-leak current in an off state, there is formed, in the vicinity of the drain region of the NMOS transistor for ESD protection, an n-type region receiving a signal from an external connection terminal via a p-type region in contact with the drain region of the NMOS transistor for ESD protection.
摘要翻译：在包括由用于器件隔离的浅沟槽围绕的用于静电放电保护的n型金属氧化物半导体晶体管的半导体器件中，为了抑制处于断开状态的漏电流，在漏极附近形成用于ESD保护的NMOS晶体管的区域，n型区域，经由与用于ESD保护的NMOS晶体管的漏极区域接触的p型区域从外部连接端子接收信号。

10. 发明申请

US20080150068A1 Image sensor IC 审中-公开
标题翻译：图像传感器IC
公开(公告)号：US20080150068A1
公开(公告)日：2008-06-26
申请号：US12004152
申请日：2007-12-19
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L31/0232
CPC分类号： H01L27/14601 , H01L27/14621
摘要： Polycrystalline silicon thin films are each fixed to the same potential and are each formed under the protective film of each of a plurality of pixel regions for receiving red light, a plurality of pixel regions for receiving green light, and a plurality of pixel regions for receiving blue light, and each polycrystalline silicon thin films has a different thickness for selectively transmitting a received light wavelength of each of the plurality of pixel regions for receiving red light, the plurality of pixel regions for receiving green light, and the plurality of pixel regions for receiving blue light to function as a color filter. The color filter can be formed during an IC manufacturing process while the color filter is positioned to align with the pixel region serving as a light receiving element, with higher precision.
摘要翻译：多晶硅薄膜各自固定成相同的电位，并且各自形成在用于接收红光的多个像素区域中的每一个的保护膜下方，用于接收绿光的多个像素区域和用于接收的多个像素区域蓝色光，并且每个多晶硅薄膜具有不同的厚度，用于选择性地透射用于接收红光的多个像素区域中的每一个的接收光波长，用于接收绿光的多个像素区域和用于接收绿光的多个像素区域接收蓝光以用作滤色器。可以在IC制造过程中形成滤色器，同时以更高的精度将滤色器定位成与用作光接收元件的像素区域对准。

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