专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08732377B2 Interconnection apparatus and controlling method therefor 有权
标题翻译：互连装置及其控制方法
公开(公告)号：US08732377B2
公开(公告)日：2014-05-20
申请号：US13296846
申请日：2011-11-15
申请人： Hiroaki Sakaguchi , Hitoshi Kai , Hiroshi Kobayashi
发明人： Hiroaki Sakaguchi , Hitoshi Kai , Hiroshi Kobayashi
IPC分类号： G06F13/372
CPC分类号： G06F13/4059 , G06F2213/0038
摘要： Certain aspects of an apparatus and method for interconnection may include an interconnection section, a request processing section and a response processing section. The interconnection section may be configured to transfer a request from a master interface bus to a slave interface bus and to transfer a response from the slave interface bus to the master interface bus. A slot number within the request specifies a time slot during which the interconnection section may be permitted to transfer the response to the master interface bus. The request commands the processing section to load the slot number into a management table. The response commands the response processing section to read out the slot number from the management table.
摘要翻译：用于互连的设备和方法的某些方面可以包括互连部分，请求处理部分和响应处理部分。互连部分可以被配置为将请求从主接口总线传送到从接口总线，并将响应从从接口总线传送到主接口总线。请求内的时隙号指定可允许互连部分将响应传送到主接口总线的时隙。请求命令处理部分将插槽号加载到管理表中。响应命令响应处理部分从管理表中读出插槽号。

2. 发明授权

US08650385B2 Instruction fetch apparatus, processor and program counter addition control method 有权
标题翻译：指令提取装置，处理器和程序计数器附加控制方法
公开(公告)号：US08650385B2
公开(公告)日：2014-02-11
申请号：US13024580
申请日：2011-02-10
申请人： Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
发明人： Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/321 , G06F9/30101 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3804 , G06F9/3842
摘要： An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.
摘要翻译：一种提取指令装置，其特征在于包括：程序计数器，被配置为在其中顺序放置属于多个指令序列的指令的程序中管理目标要执行的指令的地址; 变更指定寄存器，被配置为指定所述程序计数器上的增量值的变化; 增量值寄存器，被配置为保持所述改变的增量值; 以及附加控制部分，其被配置为使得如果所述改变指定寄存器指定所述程序计数器上的所述增量值的改变，则所述相加控制部分基于所述增量值寄存器中保持的改变的增量值来增加所述程序计数器，所述加法控制如果改变指定寄存器没有指定程序计数器上的增量值的任何改变，则进一步将程序计数器递增指令字长度。

3. 发明申请

US20120144079A1 INTERCONNECTION APPARATUS AND CONTROLLING METHOD THEREFOR 有权
标题翻译：互连装置及其控制方法
公开(公告)号：US20120144079A1
公开(公告)日：2012-06-07
申请号：US13296846
申请日：2011-11-15
申请人： Hiroaki Sakaguchi , Hitoshi Kai , Hiroshi Kobayashi
发明人： Hiroaki Sakaguchi , Hitoshi Kai , Hiroshi Kobayashi
IPC分类号： G06F13/00
CPC分类号： G06F13/4059 , G06F2213/0038
摘要： An interconnection apparatus includes: a buffer; a request processing section; a response processing section; and an interconnection section.
摘要翻译：互连装置包括：缓冲器; 请求处理部分; 响应处理部; 和互连部分。

4. 发明申请

US20110238952A1 INSTRUCTION FETCH APPARATUS, PROCESSOR AND PROGRAM COUNTER ADDITION CONTROL METHOD 有权
标题翻译：指令设备，处理器和程序计数器附加控制方法
公开(公告)号：US20110238952A1
公开(公告)日：2011-09-29
申请号：US13024580
申请日：2011-02-10
申请人： Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
发明人： Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
IPC分类号： G06F9/38
CPC分类号： G06F9/321 , G06F9/30101 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3804 , G06F9/3842
摘要： An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.
摘要翻译：一种提取指令装置，其特征在于包括：程序计数器，被配置为在其中顺序放置属于多个指令序列的指令的程序中管理目标要执行的指令的地址; 变更指定寄存器，被配置为指定所述程序计数器上的增量值的变化; 增量值寄存器，被配置为保持所述改变的增量值; 以及附加控制部分，其被配置为使得如果所述改变指定寄存器指定所述程序计数器上的所述增量值的改变，则所述相加控制部分基于所述增量值寄存器中保持的改变的增量值来增加所述程序计数器，所述加法控制如果改变指定寄存器没有指定程序计数器上的增量值的任何改变，则进一步将程序计数器递增指令字长度。

5. 发明授权

US08145875B2 Address translation circuit for a CPU 有权
标题翻译： CPU的地址转换电路
公开(公告)号：US08145875B2
公开(公告)日：2012-03-27
申请号：US12393124
申请日：2009-02-26
申请人： Hitoshi Kai
发明人： Hitoshi Kai
IPC分类号： G06F12/00
CPC分类号： G06F12/0223 , G06F12/0888 , G06F12/10
摘要： An address translation circuit includes an area address holding section, an invert flag holding section, a match detection section, and a bit conversion section. The area address holding section holds at least part of a translation target address as an area address. The invert flag holding section holds an invert flag specifying whether or not part of said translation target address is to be inverted. The match detection section detects a match between a predetermined part of at least one bit in an input address on the one hand, and said area address held by said area address holding section on the other hand. If a match is detected by said match detection section and if said invert flag held by said invert flag holding section specifies that part of said translation target address is to be inverted, the bit inversion section inverts a predetermined bit part in said input address before outputting the bit-inverted address.
摘要翻译：地址转换电路包括区域地址保持部分，反转标志保持部分，匹配检测部分和位转换部分。区域地址保持部分保存翻译目标地址的至少一部分作为区域地址。反转标志保持部分保持反转标志，指定所述转换目标地址的一部分是否被反转。匹配检测部分检测一方面的输入地址中的至少一位的预定部分与由所述区域地址保持部分保持的所述区域地址之间的匹配。如果所述匹配检测部分检测到匹配，并且如果由所述反相标志保持部分保持的所述反相标志指定所述转换目标地址的那部分将被反转，则位转换部分在输出之前将所述输入地址中的预定位部分反相位反转地址。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式