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1. 发明授权

US08709871B2 Stacked type semiconductor memory device and chip selection circuit 失效
标题翻译：堆叠型半导体存储器件和芯片选择电路
公开(公告)号：US08709871B2
公开(公告)日：2014-04-29
申请号：US13293897
申请日：2011-11-10
申请人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C2029/4402 , H01L2224/16145 , H01L2225/06513 , H01L2924/01021 , H01L2924/15311
摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
摘要翻译：通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括：多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

2. 发明申请

US20070181991A1 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US20070181991A1
公开(公告)日：2007-08-09
申请号：US11651517
申请日：2007-01-10
申请人： Masakazu Ishino , Hiroaki Ikeda , Junji Yamada
发明人： Masakazu Ishino , Hiroaki Ikeda , Junji Yamada
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06572 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.
摘要翻译：叠层半导体器件包括具有外部电源端子的内插基板和堆叠在插入器基板上的半导体芯片。布置在位于底层的半导体芯片中的电源布线通过凸块电极连接到外部电源端子，布置在位于顶层的半导体芯片中的电源布线通过外部电源端子经由接合线，并且各自布置在相邻的半导体芯片中的电源布线经由通孔相互连接。这种环路结构可以解决半导体芯片越高电压下降的问题。

3. 发明申请

US20070126105A1 Stacked type semiconductor memory device and chip selection circuit 失效
标题翻译：堆叠型半导体存储器件和芯片选择电路
公开(公告)号：US20070126105A1
公开(公告)日：2007-06-07
申请号：US11634144
申请日：2006-12-06
申请人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C2029/4402 , H01L2224/16145 , H01L2225/06513 , H01L2924/01021 , H01L2924/15311
摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
摘要翻译：通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括：多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

4. 发明申请

US20070117317A1 STACKED MEMORY 有权
标题翻译：堆叠内存
公开(公告)号：US20070117317A1
公开(公告)日：2007-05-24
申请号：US11560898
申请日：2006-11-17
申请人： Hiroaki Ikeda , Kayoko Shibata , Junji Yamada
发明人： Hiroaki Ikeda , Kayoko Shibata , Junji Yamada
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： G11C5/025
摘要： In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-oparity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.
摘要翻译：在具有通过电极的三维堆叠存储器中，没有建立最优层布置，库布置，控制方法，因此希望建立最佳方法。堆叠存储器包括存储器核心层，插入器和IF芯片。通过堆叠具有相同布置的存储器核心层，可以处理无视操作和奇偶校验操作两者。此外，可以通过分配行地址和银行地址来实现与存储器核心层的堆栈数无关的库指定。此外，IF芯片具有用于执行堆叠存储器的刷新控制的刷新计数器。这种布置提供了包括具有通过电极的堆叠的存储器芯层的堆叠存储器。

5. 发明授权

US08076764B2 Stacked type semiconductor memory device and chip selection circuit 失效
标题翻译：堆叠型半导体存储器件和芯片选择电路
公开(公告)号：US08076764B2
公开(公告)日：2011-12-13
申请号：US11634144
申请日：2006-12-06
申请人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C2029/4402 , H01L2224/16145 , H01L2225/06513 , H01L2924/01021 , H01L2924/15311
摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
摘要翻译：通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括：多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

6. 发明授权

US07531905B2 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US07531905B2
公开(公告)日：2009-05-12
申请号：US11651517
申请日：2007-01-10
申请人： Masakzau Ishino , Hiroaki Ikeda , Junji Yamada
发明人： Masakzau Ishino , Hiroaki Ikeda , Junji Yamada
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/02
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06572 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.
摘要翻译：叠层半导体器件包括具有外部电源端子的内插基板和堆叠在插入器基板上的半导体芯片。布置在位于底层的半导体芯片中的电源布线通过凸块电极连接到外部电源端子，布置在位于顶层的半导体芯片中的电源布线通过外部电源端子经由接合线，并且各自布置在相邻的半导体芯片中的电源布线经由通孔相互连接。这种环路结构可以解决半导体芯片越高电压下降的问题。

7. 发明申请

US20070228456A1 LAMINATED MEMORY HAVING AUTONOMICALLY AND SEQUENTIALLY ACTIVATING OPERATION 失效
标题翻译：具有自动和顺序激活操作的层压记忆体
公开(公告)号：US20070228456A1
公开(公告)日：2007-10-04
申请号：US11690032
申请日：2007-03-22
申请人： Hiroaki Ikeda , Junji Yamada
发明人： Hiroaki Ikeda , Junji Yamada
IPC分类号： H01L29/792
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L27/0688 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： In a laminated memory, each of memory core layers includes a delay circuit having a period of delay time corresponding to a period of operation time of an internal memory circuit portion thereof. A memory core layer, which is input with a simultaneous operation signal, operates in response to the input operation signal. The delay circuit includes an autonomically and sequentially activating function for sending an operation signal to a next stage after the period of delay time passes.
摘要翻译：在层叠存储器中，每个存储核心层包括具有对应于其内部存储器电路部分的操作时间周期的延迟时间的延迟电路。输入同时操作信号的存储核心层响应于输入操作信号而工作。延迟电路包括在延迟时间过去之后将操作信号发送到下一级的自动和顺序启动功能。

8. 发明授权

US07894293B2 Memory bank arrangement for stacked memory 有权
标题翻译：存储器堆栈堆叠存储器
公开(公告)号：US07894293B2
公开(公告)日：2011-02-22
申请号：US11560898
申请日：2006-11-17
申请人： Hiroaki Ikeda , Kayoko Shibata , Junji Yamada
发明人： Hiroaki Ikeda , Kayoko Shibata , Junji Yamada
IPC分类号： G11C8/00
CPC分类号： G11C5/025
摘要： In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-parity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.
摘要翻译：在具有通过电极的三维堆叠存储器中，没有建立最优层布置，库布置，控制方法，因此希望建立最佳方法。堆叠存储器包括存储器核心层，插入器和IF芯片。通过堆叠具有相同配置的存储器核心层，可以处理无奇偶校验操作和奇偶校验操作两者。此外，可以通过分配行地址和银行地址来实现与存储器核心层的堆栈数无关的库指定。此外，IF芯片具有用于执行堆叠存储器的刷新控制的刷新计数器。这种布置提供了包括具有通过电极的堆叠的存储器芯层的堆叠存储器。

9. 发明授权

US07483317B2 Laminated memory having autonomically and sequentially activating operation 失效
标题翻译：具有自主且依次激活操作的层压存储器
公开(公告)号：US07483317B2
公开(公告)日：2009-01-27
申请号：US11690032
申请日：2007-03-22
申请人： Hiroaki Ikeda , Junji Yamada
发明人： Hiroaki Ikeda , Junji Yamada
IPC分类号： G11C11/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L27/0688 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： In a laminated memory, each of memory core layers includes a delay circuit having a period of delay time corresponding to a period of operation time of an internal memory circuit portion thereof. A memory core layer, which is input with a simultaneous operation signal, operates in response to the input operation signal. The delay circuit includes an autonomically and sequentially activating function for sending an operation signal to a next stage after the period of delay time passes.
摘要翻译：在层叠存储器中，每个存储核心层包括具有对应于其内部存储器电路部分的操作时间周期的延迟时间的延迟电路。输入同时操作信号的存储核心层响应于输入操作信号而工作。延迟电路包括在延迟时间过去之后将操作信号发送到下一级的自动和顺序启动功能。

10. 发明授权

US09516192B2 Image forming method for increasing resolution in reverse mode 有权
标题翻译：用于在反向模式下增加分辨率的成像方法
公开(公告)号：US09516192B2
公开(公告)日：2016-12-06
申请号：US14024003
申请日：2013-09-11
申请人： Masayuki Hayashi , Yoshinori Shirasaki , Tatsuya Miyadera , Motohiro Kawanabe , Hiroaki Ikeda , Akinori Yamaguchi , Tomohiro Ohshima
发明人： Masayuki Hayashi , Yoshinori Shirasaki , Tatsuya Miyadera , Motohiro Kawanabe , Hiroaki Ikeda , Akinori Yamaguchi , Tomohiro Ohshima
IPC分类号： H04N1/40
CPC分类号： H04N1/40068
摘要： An image forming apparatus comprising: a resolution conversion unit configured to convert the resolution of a pixel provided by input image data; a gradation conversion unit configured to perform matrix conversion onto the pixel; and a writing unit configured to perform a write operation, wherein, in the normal mode, the gradation conversion unit performs matrix conversion onto the pixel with reference to the gradation conversion table for the normal mode, and the writing unit performs the write operation of the pixel in a normal order that is the order image data being input into the image forming apparatus, and in the reverse mode, the gradation conversion unit performs matrix conversion onto the pixel with reference to the gradation conversion table for the reverse mode, and the writing unit performs the write operation of the pixel in a reverse order opposite to the normal order.
摘要翻译：一种图像形成装置，包括：分辨率转换单元，被配置为转换由输入图像数据提供的像素的分辨率; 灰度转换单元，被配置为对所述像素执行矩阵转换; 以及写入单元，被配置为执行写入操作，其中在所述正常模式中，所述灰度转换单元参照用于所述正常模式的灰度转换表，对所述像素执行矩阵转换，并且所述写入单元执行所述写入操作以顺序图像数据输入到图像形成装置中的正常顺序的像素，并且在反向模式中，灰度转换单元参照用于反向模式的灰度转换表，对像素执行矩阵转换，并且写入单元以与正常顺序相反的相反顺序执行像素的写入操作。

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