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1. 发明授权

US06788608B2 High voltage pulse method and apparatus for digital multilevel non-volatile memory integrated system 有权
标题翻译：数字多电平非易失性存储器集成系统的高压脉冲法和装置
公开(公告)号：US06788608B2
公开(公告)日：2004-09-07
申请号：US10209538
申请日：2002-07-30
申请人： Hieu Van Tran , William John Saiki , Jack Edward Frayer , Michael Stephen Briner
发明人： Hieu Van Tran , William John Saiki , Jack Edward Frayer , Michael Stephen Briner
IPC分类号： G11C700
CPC分类号： G11C5/145 , G11C11/56 , G11C16/30
摘要： A digital multilevel non-volatile memory integrated system includes an apparatus and method for high voltage, high precision pulsing generation. A voltage generator includes a low voltage high speed generator, a low voltage to high voltage high speed level translator, and a high voltage driver. A precise and stable high voltage level is attained across power supply, process, or temperature variation. The power may be optimized at the high voltage supply as tradeoff with power in the low voltage supply. A ping-pong operation sets up a high voltage level and the high voltage pulsing is output in a ping-pong fashion. A slew rate control circuit slows the input to achieve faster settling times. The high voltage is shaped by low voltage switching, HV fast switching and ramp circuit control. The high voltage pulsing may be fast and precise to permit real time control of the pulse parameters to adapt to memory cell attributes.
摘要翻译：数字多电平非易失性存储器集成系统包括用于高电压，高精度脉冲发生的装置和方法。电压发生器包括低压高速发生器，低压至高压高速电平转换器和高压驱动器。通过电源，过程或温度变化实现精确稳定的高电压电平。功率可以在高压电源下进行优化，因为在低电压电源中与功率进行权衡。乒乓操作设置高电压电平，高压脉冲以乒乓方式输出。转换速率控制电路减慢输入以实现更快的建立时间。高压通过低压开关，高压快速开关和斜坡电路控制形成。高压脉冲可以是快速和精确的，以允许脉冲参数的实时控制以适应存储器单元属性。

2. 发明授权

US07184345B2 High speed and high precision sensing for digital multilevel non-volatile memory system 有权
标题翻译：数字多级非易失性存储器系统的高速和高精度感测
公开(公告)号：US07184345B2
公开(公告)日：2007-02-27
申请号：US11283195
申请日：2005-11-18
申请人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
发明人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
摘要翻译：数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。高速负载提供高速感应。宽输出范围在比较节点上提供高速的感测余量。低阻抗输出驱动器驱动差分比较器的高噪声负载。耦合到读出放大器的输入和输出的预充电电路增加了感测速度。差分比较器具有包括模拟引导的架构。参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

3. 发明授权

US06885600B2 Differential sense amplifier for multilevel non-volatile memory 有权
标题翻译：差分放大器用于多电平非易失性存储器
公开(公告)号：US06885600B2
公开(公告)日：2005-04-26
申请号：US10241266
申请日：2002-09-10
申请人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
发明人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
IPC分类号： G11C7/06 , G11C11/56 , G11C16/28 , G11C17/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/065 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
摘要翻译：数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。高速负载提供高速感应。宽输出范围在比较节点上提供高速的感测余量。低阻抗输出驱动器驱动差分比较器的高噪声负载。耦合到读出放大器的输入和输出的预充电电路增加了感测速度。差分比较器具有包括模拟引导的架构。参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

4. 发明授权

US07038960B2 High speed and high precision sensing for digital multilevel non-volatile memory system 有权
标题翻译：数字多级非易失性存储器系统的高速和高精度感测
公开(公告)号：US07038960B2
公开(公告)日：2006-05-02
申请号：US10241442
申请日：2002-09-10
申请人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
发明人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
摘要翻译：数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。高速负载提供高速感应。宽输出范围在比较节点上提供高速的感测余量。低阻抗输出驱动器驱动差分比较器的高噪声负载。耦合到读出放大器的输入和输出的预充电电路增加了感测速度。差分比较器具有包括模拟引导的架构。参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

5. 发明授权

US07403418B2 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US07403418B2
公开(公告)日：2008-07-22
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

6. 发明授权

US07439572B2 Stacked gate memory cell with erase to gate, array, and method of manufacturing 有权
标题翻译：具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
公开(公告)号：US07439572B2
公开(公告)日：2008-10-21
申请号：US11303567
申请日：2005-12-15
申请人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
发明人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/7885
摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
摘要翻译：堆叠式非易失性存储器浮栅器件具有控制栅极。通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。最后，为了增加密度，可以在沟槽中制造每个单元。

7. 发明授权

US07242050B2 Stacked gate memory cell with erase to gate, array, and method of manufacturing 有权
标题翻译：具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
公开(公告)号：US07242050B2
公开(公告)日：2007-07-10
申请号：US10714243
申请日：2003-11-13
申请人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
发明人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/7885
摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
摘要翻译：堆叠式非易失性存储器浮栅器件具有控制栅极。通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。最后，为了增加密度，可以在沟槽中制造每个单元。

8. 发明授权

US08954822B2 Data encoder and decoder using memory-specific parity-check matrix 有权
标题翻译：数据编码器和解码器使用特定于存储器的奇偶校验矩阵
公开(公告)号：US08954822B2
公开(公告)日：2015-02-10
申请号：US13679970
申请日：2012-11-16
申请人： Jack Edward Frayer , Aaron K. Olbrich
发明人： Jack Edward Frayer , Aaron K. Olbrich
IPC分类号： G11C29/00 , H03M13/13 , G06F11/10
CPC分类号： H03M13/13 , G06F11/1012 , H03M13/1102 , H03M13/152 , H03M13/2906 , H03M13/2948 , H03M13/356
摘要： An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.
摘要翻译：错误控制系统使用对应于存储介质的错误密度位置简档的错误控制代码。该系统包括编码器，其被配置为使用与存储介质的误差密度位置分布相对应的误差控制码发生器矩阵从数据产生一个或多个码字。该系统还包括解码器，其被配置为使用对应于存储介质的误差密度位置简档的误差控制码奇偶校验矩阵从一个或多个码字产生解码数据，其中奇偶校验矩阵的列与相应的数据相关联存储介质的位，奇偶校验矩阵的行与校验位相关联，并且具有预定义值的奇偶校验矩阵的每个矩阵元素指示特定数据位和特定校验位之间的连接。

9. 发明申请

US20120324276A1 INTELLIGENT BIT RECOVERY FOR FLASH MEMORY 有权
标题翻译：用于闪存存储器的智能位恢复
公开(公告)号：US20120324276A1
公开(公告)日：2012-12-20
申请号：US13285873
申请日：2011-10-31
申请人： Jack Edward Frayer , Aaron Keith Olbrich , Paul Roger Stonelake , Anand Krishnamurthi Kulkarni , Yale Yueh Ma
发明人： Jack Edward Frayer , Aaron Keith Olbrich , Paul Roger Stonelake , Anand Krishnamurthi Kulkarni , Yale Yueh Ma
IPC分类号： G06F11/16
CPC分类号： G11C16/3427 , G11C11/5642 , G11C16/26 , G11C16/3422
摘要： A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.
摘要翻译：提供了一种方法和系统智能位恢复。智能位恢复确定哪些位正在切换，并且检查潜在位模式的子集以确定潜在位模式的子集中哪一个是有效的。该子集是潜在位模式的一小部分，并且基于对闪存的理解以及可能导致切换位的问题。智能位恢复可以分析闪速存储器的至少一个方面以识别哪个问题潜在地导致切换位，并且选择潜在位模式的子集作为所确定问题的解决方案。或者，智能位恢复为潜在的潜在问题选择潜在的位模式。以任一方式，通过智能位恢复检查的潜在位模式的子集是整个潜在位模式集合的一小部分。

10. 发明申请

US20080114924A1 High bandwidth distributed computing solid state memory storage system 审中-公开
标题翻译：高带宽分布式计算固态存储系统
公开(公告)号：US20080114924A1
公开(公告)日：2008-05-15
申请号：US11982544
申请日：2007-11-02
申请人： Jack Edward Frayer , Y. Y. Ma
发明人： Jack Edward Frayer , Y. Y. Ma
IPC分类号： G06F12/02 , G06F13/14
CPC分类号： G06F13/4239 , G06F3/0613 , G06F3/0619 , G06F3/0625 , G06F3/0656 , G06F3/0679 , G06F12/0866 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/154
摘要： Embodiments of the present invention provides a system controller interfacing point-to-point subsystems consisting of solid state memory. The point-to-point linked subsystems enable high bandwidth data transfer to a system controller. The memory subsystems locally control the normal solid state disk functions. The independent subsystems thus configured and scaled according to various applications enables the memory storage system to operate with optimal data bandwidths, optimal overall power consumption, improved data integrity and increased disk capacity than previous solid state disk implementations.
摘要翻译：本发明的实施例提供一种由固态存储器组成的系统控制器接口点对点子系统。点到点链接的子系统使得能够将高带宽数据传输到系统控制器。内存子系统本地控制正常的固态磁盘功能。如此根据各种应用配置和缩放的独立子系统使得存储器存储系统能够以比先前的固态磁盘实现更好的数据带宽，最佳的整体功耗，改进的数据完整性和增加的磁盘容量来运行。

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