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1. 发明授权

US07816782B2 Wiring substrate for mounting semiconductors, method of manufacturing the same, and semiconductor package 有权
标题翻译：用于安装半导体的接线基板，其制造方法和半导体封装
公开(公告)号：US07816782B2
公开(公告)日：2010-10-19
申请号：US11174526
申请日：2005-07-06
申请人： Hideya Murai , Tadanori Shimoto , Takuo Funaya , Katsumi Kikuchi , Shintaro Yamamichi , Kazuhiro Baba , Hirokazu Honda , Keiichiro Kata , Kouji Matsui , Shinichi Miyazaki
发明人： Hideya Murai , Tadanori Shimoto , Takuo Funaya , Katsumi Kikuchi , Shintaro Yamamichi , Kazuhiro Baba , Hirokazu Honda , Keiichiro Kata , Kouji Matsui , Shinichi Miyazaki
IPC分类号： H01L23/14 , H01L23/12
CPC分类号： H01L21/4857 , H01L23/49822 , H01L23/49833 , H01L23/5383 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/45144 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/181 , H05K3/007 , H05K3/205 , H05K3/28 , H05K3/4614 , H05K3/4682 , H05K2201/0376 , H05K2203/0152 , H05K2203/061 , H01L2224/05599 , H01L2924/00012
摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.
摘要翻译：用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去金属板。

2. 发明申请

US20060012048A1 Wiring substrate for mounting semiconductors, method of manufacturing the same, and semiconductor package 有权
标题翻译：用于安装半导体的接线基板，其制造方法和半导体封装
公开(公告)号：US20060012048A1
公开(公告)日：2006-01-19
申请号：US11174526
申请日：2005-07-06
申请人： Hideya Murai , Tadanori Shimoto , Takuo Funaya , Katsumi Kikuchi , Shintaro Yamamichi , Kazuhiro Baba , Hirokazu Honda , Keiichiro Kata , Kouji Matsui , Shinichi Miyazaki
发明人： Hideya Murai , Tadanori Shimoto , Takuo Funaya , Katsumi Kikuchi , Shintaro Yamamichi , Kazuhiro Baba , Hirokazu Honda , Keiichiro Kata , Kouji Matsui , Shinichi Miyazaki
IPC分类号： H01L23/48
CPC分类号： H01L21/4857 , H01L23/49822 , H01L23/49833 , H01L23/5383 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/45144 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/181 , H05K3/007 , H05K3/205 , H05K3/28 , H05K3/4614 , H05K3/4682 , H05K2201/0376 , H05K2203/0152 , H05K2203/061 , H01L2224/05599 , H01L2924/00012
摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.
摘要翻译：用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去金属板。

3. 发明授权

US08198140B2 Wiring substrate for mounting semiconductors, method of manufacturing the same, and semiconductor package 有权
标题翻译：用于安装半导体的接线基板，其制造方法和半导体封装
公开(公告)号：US08198140B2
公开(公告)日：2012-06-12
申请号：US12882277
申请日：2010-09-15
申请人： Hideya Murai , Tadanori Shimoto , Takuo Funaya , Katsumi Kikuchi , Shintaro Yamamichi , Kazuhiro Baba , Hirokazu Honda , Keiichiro Kata , Kouji Matsui , Shinichi Miyazaki
发明人： Hideya Murai , Tadanori Shimoto , Takuo Funaya , Katsumi Kikuchi , Shintaro Yamamichi , Kazuhiro Baba , Hirokazu Honda , Keiichiro Kata , Kouji Matsui , Shinichi Miyazaki
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L21/4857 , H01L23/49822 , H01L23/49833 , H01L23/5383 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/45144 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/181 , H05K3/007 , H05K3/205 , H05K3/28 , H05K3/4614 , H05K3/4682 , H05K2201/0376 , H05K2203/0152 , H05K2203/061 , H01L2224/05599 , H01L2924/00012
摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.
摘要翻译：用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去金属板。

4. 发明申请

US20090046441A1 WIRING BOARD FOR MOUNTING SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SAME, AND WIRING BOARD ASSEMBLY 审中-公开
标题翻译：用于安装半导体器件的接线板及其制造方法和接线板组件
公开(公告)号：US20090046441A1
公开(公告)日：2009-02-19
申请号：US12160132
申请日：2006-12-20
申请人： Takuo Funaya , Hideya Murai , Shintaro Yamamichi , Katsumi Kikuchi , Hirokazu Honda , Shinichi Miyazaki
发明人： Takuo Funaya , Hideya Murai , Shintaro Yamamichi , Katsumi Kikuchi , Hirokazu Honda , Shinichi Miyazaki
IPC分类号： H05K1/11 , H05K1/18
CPC分类号： H01L21/6835 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49866 , H01L24/45 , H01L24/48 , H01L2221/68345 , H01L2221/68359 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/09701 , H01L2924/12041 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/19041 , H05K1/115 , H05K1/117 , H05K3/20 , H05K3/4614 , H05K3/4682 , H05K3/4694 , H05K2201/0272 , H05K2201/0352 , H05K2201/09845 , H05K2201/09972 , H05K2203/0425 , H05K2203/061 , H01L2924/00 , H01L2224/05599
摘要： A wiring board for mounting semiconductor device, includes at least a dielectric film 1; wirings formed in the dielectric film 1; a plurality of electrode pads provided at front and back surfaces of the dielectric film with their surfaces exposed and at least portions of lateral sides of them buried into the dielectric film; vias connecting the wirings and the electrode pads. At least one via connecting each other the wirings formed in the dielectric film includes second material different from first material forming the vias connecting the wirings and the electrode pads. The wiring board for mounting semiconductor device, is effective for an increase in terminals and finer pitch of terminal intervals due to an improvement in integration, performance or multi-function of semiconductor devices, can mount semiconductor devices especially on both sides of the board at a high density and high accuracy, and furthermore, is excellent in reliability as well.
摘要翻译：一种用于安装半导体器件的布线板，至少包括电介质膜1; 电介质膜1中形成的布线; 多个电极焊盘，其设置在电介质膜的前表面和后表面，其表面暴露，并且其侧面的至少一部分埋入电介质膜中; 连接布线和电极垫的通孔。至少一个彼此连接的通孔形成在电介质膜中的布线包括与形成连接布线和电极焊盘的通孔的第一材料不同的第二材料。用于安装半导体器件的布线板，由于半导体器件的集成度，性能或多功能性的提高，端子间距的增加和端子间隔的更细的间距是有效的，所以可以在半导体器件的两侧特别地安装半导体器件高密度和高精度，此外，也具有优异的可靠性。

5. 发明授权

US07348673B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07348673B2
公开(公告)日：2008-03-25
申请号：US11180729
申请日：2005-07-14
申请人： Katsumi Kikuchi , Shintaro Yamamichi , Hideya Murai , Hirokazu Honda , Koji Soejima , Shinichi Miyazaki
发明人： Katsumi Kikuchi , Shintaro Yamamichi , Hideya Murai , Hirokazu Honda , Koji Soejima , Shinichi Miyazaki
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/3114 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C. is not more than that of the second insulating layers, each of the third wiring layers and each of the third insulating layers being alternately laminated.
摘要翻译：在半导体基板上形成包括第一布线层和第一绝缘层的微小布线结构部分，其中第一布线层和每个第一绝缘层交替层叠。第一巨型布线结构部分形成在微小布线结构部分上，并且第一巨大的布线结构部分通过在微小的布线结构部分上依次形成，按照以下顺序形成包括第二布线层的第一巨大布线部分具有其中第二布线层和每个第二布线层交替层叠的第一布线层和第二绝缘层的厚度的两倍或更多的厚度，以及包括第三布线层的第二巨大布线结构部分的厚度为第一布线层的厚度的2倍以上，25℃下的弹性模量不大于第2绝缘层的弹性模量的第3绝缘层，第3布线层和第3绝缘层交替层压。

6. 发明申请

US20060012029A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060012029A1
公开(公告)日：2006-01-19
申请号：US11180729
申请日：2005-07-14
申请人： Katsumi Kikuchi , Shintaro Yamamichi , Hideya Murai , Hirokazu Honda , Koji Soejima , Shinichi Miyazaki
发明人： Katsumi Kikuchi , Shintaro Yamamichi , Hideya Murai , Hirokazu Honda , Koji Soejima , Shinichi Miyazaki
IPC分类号： H01L23/12
CPC分类号： H01L23/528 , H01L23/3114 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C. is not more than that of the second insulating layers, each of the third wiring layers and each of the third insulating layers being alternately laminated.
摘要翻译：在半导体基板上形成包括第一布线层和第一绝缘层的微小布线结构部分，其中第一布线层和每个第一绝缘层交替层叠。第一巨型布线结构部分形成在微小布线结构部分上，并且第一巨大的布线结构部分通过在微小的布线结构部分上依次形成，按照以下顺序形成包括第二布线层的第一巨大布线部分具有其中第二布线层和每个第二布线层交替层叠的第一布线层和第二绝缘层的厚度的两倍或更多的厚度，以及包括第三布线层的第二巨大布线结构部分的厚度为第一布线层的厚度的2倍以上，25℃下的弹性模量不大于第2绝缘层的弹性模量的第3绝缘层，第3布线层和第3绝缘层交替层压。

7. 发明授权

US07498249B2 Method of forming a connecting conductor and wirings of a semiconductor chip 有权
标题翻译：形成半导体芯片的连接导体和布线的方法
公开(公告)号：US07498249B2
公开(公告)日：2009-03-03
申请号：US11521354
申请日：2006-09-15
申请人： Shinichi Miyazaki , Hirokazu Honda , Kenji Ooyachi
发明人： Shinichi Miyazaki , Hirokazu Honda , Kenji Ooyachi
IPC分类号： H01L21/44
CPC分类号： H01L23/3107 , H01L21/568 , H01L24/19 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68345 , H01L2224/24226 , H01L2224/32014 , H01L2224/82047 , H01L2225/1035 , H01L2225/1058 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18162 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist post being exposed. The exposed resist post is then removed by developing processing or the like, thus forming a through hole. A conductor is then embedded in the through hole by plating, thus forming a connecting conductor, and wirings are formed. A method of forming the connecting conductor does not impart damage to the semiconductor chip.
摘要翻译：在半导体芯片的连接焊盘上形成抗蚀剂柱，半导体芯片和抗蚀剂柱被耐热绝缘层覆盖。然后通过CMP等对绝缘层的表面进行抛光，从而使抗蚀剂柱的上表面露出。然后通过显影处理等去除曝光的抗蚀剂柱，从而形成通孔。然后通过电镀将导体嵌入通孔中，从而形成连接导体，并且形成布线。形成连接导体的方法不会对半导体芯片产生损害。

8. 发明申请

US20070020907A1 Method of forming a connecting conductor and wirings of a semiconductor chip 有权
标题翻译：形成半导体芯片的连接导体和布线的方法
公开(公告)号：US20070020907A1
公开(公告)日：2007-01-25
申请号：US11521354
申请日：2006-09-15
申请人： Shinichi Miyazaki , Hirokazu Honda , Kenji Ooyachi
发明人： Shinichi Miyazaki , Hirokazu Honda , Kenji Ooyachi
IPC分类号： H01L21/44
CPC分类号： H01L23/3107 , H01L21/568 , H01L24/19 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68345 , H01L2224/24226 , H01L2224/32014 , H01L2224/82047 , H01L2225/1035 , H01L2225/1058 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18162 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist post being exposed. The exposed resist post is then removed by developing processing or the like, thus forming a through hole. A conductor is then embedded in the through hole by plating, thus forming a connecting conductor, and wirings are formed. A method of forming the connecting conductor does not impart damage to the semiconductor chip.
摘要翻译：在半导体芯片的连接焊盘上形成抗蚀剂柱，半导体芯片和抗蚀剂柱被耐热绝缘层覆盖。然后通过CMP等对绝缘层的表面进行抛光，从而使抗蚀剂柱的上表面露出。然后通过显影处理等去除曝光的抗蚀剂柱，从而形成通孔。然后通过电镀将导体嵌入到通孔中，从而形成连接导体，并且形成布线。形成连接导体的方法不会对半导体芯片产生损害。

9. 发明授权

US09250641B2 Load driving circuit and load driving method 有权
标题翻译：负载驱动电路和负载驱动方式
公开(公告)号：US09250641B2
公开(公告)日：2016-02-02
申请号：US13211110
申请日：2011-08-16
申请人： Shinichi Miyazaki , Katsunori Yamazaki , Hiroyuki Yoshino , Kinya Matsuzawa , Shoichi Iino
发明人： Shinichi Miyazaki , Katsunori Yamazaki , Hiroyuki Yoshino , Kinya Matsuzawa , Shoichi Iino
IPC分类号： H02J1/00 , H02M3/02 , G05F1/56
CPC分类号： G05F1/56 , Y10T307/647 , Y10T307/675 , Y10T307/68 , Y10T307/696 , Y10T307/724 , Y10T307/729 , Y10T307/735
摘要： A load driving circuit that generates a desired voltage waveform to drive a load includes a target voltage waveform output section that outputs a target voltage waveform to be applied to the load. Power supply sections generate electrical power with voltage values different from each other. Negative feedback control sections between the power supply sections and the load supply electrical power from the corresponding power supply sections to the load and execute negative feedback control of a value of a voltage applied to the load for matching the voltage value and the target voltage waveform. A power supply connection section selects one of the power supply sections based on the value of the voltage applied to the load or the voltage value of the target voltage waveform and connects the selected power supply section to the load and disconnects the rest of the power supply sections from the load.
摘要翻译：产生用于驱动负载的期望电压波形的负载驱动电路包括输出要施加到负载的目标电压波形的目标电压波形输出部。电源部分产生彼此不同电压值的电力。电源部分之间的负反馈控制部分和从相应的电源部分到负载的负载供电，并且对施加到负载的电压值进行负反馈控制，以匹配电压值和目标电压波形。电源连接部分基于施加到负载的电压的值或目标电压波形的电压值来选择一个电源部分，并且将所选择的电源部分连接到负载并断开电源的其余部分来自负载的部分。

10. 发明授权

US09102141B2 Capacitive load driving circuit, ink jet printer, and fluid ejecting apparatus 有权
标题翻译：电容式负载驱动电路，喷墨打印机和流体喷射装置
公开(公告)号：US09102141B2
公开(公告)日：2015-08-11
申请号：US13075429
申请日：2011-03-30
申请人： Hiroyuki Yoshino , Atsushi Oshima , Kunio Tabata , Shinichi Miyazaki , Noritaka Ide
发明人： Hiroyuki Yoshino , Atsushi Oshima , Kunio Tabata , Shinichi Miyazaki , Noritaka Ide
IPC分类号： B41J29/38 , A61B17/3203 , B41J2/015 , B41J2/04 , B41J2/045 , H03F3/38 , H03F3/217 , H03F1/04 , H03F1/34 , H03K7/08
CPC分类号： B41J2/0455 , A61B17/3203 , B41J2/04541 , B41J2/04581 , B41J2/04588 , B41J2/04593 , B41J2/04596
摘要： A capacitive load driving circuit includes: a drive waveform signal generator that generates a drive waveform signal; a subtractor that outputs a differential signal between the drive waveform signal and a feedback signal; a modulator that pulse-modulates the differential signal and outputs a modulated signal; a digital power amplifier that amplifies the power of the modulated signal and outputs a power-amplified modulated signal; a smoothing filter that smoothes the power-amplified modulated signal, and outputs a drive signal of the capacitive load; a compensator that causes a phase to precede the drive signal; and an attenuator that attenuates signal amplitude in a band at least including a modulation frequency of the modulated signal. A signal output from a connecting point between the inductor and the wire is made to pass through the compensator and the attenuator and is then used as a feedback signal to the subtractor.
摘要翻译：电容性负载驱动电路包括：驱动波形信号发生器，其产生驱动波形信号; 减法器，其在所述驱动波形信号和反馈信号之间输出差分信号; 调制器，对所述差分信号进行脉冲调制并输出调制信号; 数字功率放大器，其放大调制信号的功率并输出功率放大调制信号; 平滑滤波器，其对功率放大调制信号进行平滑，并输出电容性负载的驱动信号; 使相位超前于驱动信号的补偿器; 以及衰减器，其衰减至少包括调制信号的调制频率的频带中的信号幅度。从电感器和导线之间的连接点输出的信号通过补偿器和衰减器，然后被用作到减法器的反馈信号。

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