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1. 发明授权

US09130051B2 Semiconductor device including semiconductor layer over insulating layer and manufacturing method thereof 有权
标题翻译：包括绝缘层上的半导体层的半导体器件及其制造方法
公开(公告)号：US09130051B2
公开(公告)日：2015-09-08
申请号：US13402212
申请日：2012-02-22
申请人： Hideto Ohnuma , Atsuo Isobe , Hiromichi Godo
发明人： Hideto Ohnuma , Atsuo Isobe , Hiromichi Godo
IPC分类号： H01L29/786 , H01L27/12 , H01L21/02
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02675 , H01L21/02691 , H01L27/1281
摘要： A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.
摘要翻译：示出了具有低亚阈值摆动和抑制导通电流下降的高响应性薄膜晶体管（TFT）的半导体器件及其制造方法。本发明的TFT的特征在于其源极区域或漏极区域的厚度大于沟道形成区域的厚度的半导体层。通过在突起部分和凹陷部分上形成非晶半导体层来容易地实现TFT的制造，随后对半导体层进行熔化处理，形成具有不同厚度的晶体半导体层。选择性地向半导体层的厚部分添加杂质提供了沟道形成区域比源区或漏区更薄的半导体层。

2. 发明申请

US20080220570A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080220570A1
公开(公告)日：2008-09-11
申请号：US12073618
申请日：2008-03-07
申请人： Hideto Ohnuma , Atsuo Isobe , Hiromichi Godo
发明人： Hideto Ohnuma , Atsuo Isobe , Hiromichi Godo
IPC分类号： H01L21/84
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02675 , H01L21/02691 , H01L27/1281
摘要： A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The THF of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.
摘要翻译：示出了具有低亚阈值摆动和抑制导通电流下降的高响应性薄膜晶体管（TFT）的半导体器件及其制造方法。本发明的THF的特征在于其源区域或漏极区域的厚度大于沟道形成区域的厚度的半导体层。通过在突起部分和凹陷部分上形成非晶半导体层来容易地实现TFT的制造，随后对半导体层进行熔化处理，形成具有不同厚度的晶体半导体层。选择性地向半导体层的厚部分添加杂质提供了沟道形成区域比源区或漏区更薄的半导体层。

3. 发明授权

US08143118B2 TFT device with channel region above convex insulator portions and source/drain in concave between convex insulator portions 有权
标题翻译： TFT器件，其沟槽区域位于凸形绝缘体部分之上，并且在凸形绝缘体部分之间的凹陷中的源极/漏极
公开(公告)号：US08143118B2
公开(公告)日：2012-03-27
申请号：US12073618
申请日：2008-03-07
申请人： Hideto Ohnuma , Atsuo Isobe , Hiromichi Godo
发明人： Hideto Ohnuma , Atsuo Isobe , Hiromichi Godo
IPC分类号： H01L21/84
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02675 , H01L21/02691 , H01L27/1281
摘要： A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.
摘要翻译：示出了具有低亚阈值摆动和抑制导通电流下降的高响应性薄膜晶体管（TFT）的半导体器件及其制造方法。本发明的TFT的特征在于其源极区域或漏极区域的厚度大于沟道形成区域的厚度的半导体层。通过在突起部分和凹陷部分上形成非晶半导体层来容易地实现TFT的制造，随后对半导体层进行熔化处理，形成具有不同厚度的晶体半导体层。选择性地向半导体层的厚部分添加杂质提供了沟道形成区域比源区或漏区更薄的半导体层。

4. 发明授权

US08581309B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08581309B2
公开(公告)日：2013-11-12
申请号：US13277489
申请日：2011-10-20
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
IPC分类号： H01L27/092
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

5. 发明授权

US08044464B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08044464B2
公开(公告)日：2011-10-25
申请号：US12209739
申请日：2008-09-12
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
IPC分类号： H01L27/01
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管与可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

6. 发明授权

US07982250B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07982250B2
公开(公告)日：2011-07-19
申请号：US12209696
申请日：2008-09-12
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
IPC分类号： H01L27/12
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2924/00011 , H01L2924/00014 , H01L2224/29099 , H01L2224/13099 , H01L2224/80001
摘要： A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.
摘要翻译：示出了一种半导体器件，其中在具有绝缘表面的衬底上层叠多个场效应晶体管，层间绝缘层介于其间。多个场效应晶体管中的每一个具有半导体层，该半导体层通过包括将半导体层与半导体衬底分离并随后在衬底上结合的工艺制备。多个场效应晶体管中的每一个被覆盖有提供半导体层失真的绝缘膜。此外，将半导体层的与其晶面平行的晶轴设定为半导体层的沟道长度方向，能够制造具有SOI结构的高性能，低功耗的半导体器件。

7. 发明授权

US07692194B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07692194B2
公开(公告)日：2010-04-06
申请号：US12015362
申请日：2008-01-16
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo
IPC分类号： H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78618 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a novel structure by which the operating characteristics and reliability are improved and a manufacturing method thereof. An island-shaped semiconductor layer provided over a substrate, including a channel formation region provided between a pair of impurity regions; a first insulating layer provided so as to be in contact with the side surface of the semiconductor layer; a gate electrode provided over the channel formation region so as to get across the semiconductor layer; and a second insulating layer provided between the channel formation region and the gate electrode are included. The semiconductor layer is locally thinned, the channel formation region is provided in the thinned region, and the second insulating layer covers the first insulating layer provided on the side surface of the semiconductor layer at least in the region which overlaps with the gate electrode.
摘要翻译：具有改善其操作特性和可靠性的新颖结构的半导体器件及其制造方法。一种岛状半导体层，设置在衬底上，包括设置在一对杂质区之间的沟道形成区; 设置成与半导体层的侧表面接触的第一绝缘层; 栅电极，设置在所述沟道形成区上方以穿过所述半导体层; 并且包括设置在沟道形成区域和栅电极之间的第二绝缘层。半导体层被局部变薄，沟道形成区域设置在减薄区域中，并且第二绝缘层至少在与栅电极重叠的区域中覆盖设置在半导体层的侧表面上的第一绝缘层。

8. 发明申请

US20060071210A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060071210A1
公开(公告)日：2006-04-06
申请号：US11148289
申请日：2005-06-09
申请人： Shunpei Yamazaki , Atsuo Isobe , Tetsuji Yamaguchi , Hiromichi Godo
发明人： Shunpei Yamazaki , Atsuo Isobe , Tetsuji Yamaguchi , Hiromichi Godo
IPC分类号： H01L31/0376
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1285 , H01L27/1288 , H01L27/13 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78624
摘要： It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher yield at lower cost. In the present invention, a lightly doped impurity region is formed in a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer in a thin film transistor. The semiconductor layer is doped diagonally to the surface thereof using the gate electrode layer as a mask to form the lightly doped impurity region. Therefore, the properties of the thin film transistor can be minutely controlled.
摘要翻译：本发明的目的是制造具有所需性能的薄膜晶体管，而不会使步骤和装置复杂化。本发明的另一个目的是提供一种以更低的成本制造具有高可靠性和更好的电气特性并以较高产量获得的半导体器件的技术。在本发明中，在薄膜晶体管中由栅极电极层覆盖的半导体层的源区域侧或漏极区侧形成有轻掺杂杂质区。使用栅极电极层作为掩模将半导体层以其对面的方式对角地掺杂以形成轻掺杂杂质区域。因此，可以精细地控制薄膜晶体管的性质。

9. 发明申请

US20050274952A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050274952A1
公开(公告)日：2005-12-15
申请号：US11148426
申请日：2005-06-09
申请人： Shunpei Yamazaki , Atsuo Isobe , Tetsuji Yamaguchi , Hiromichi Godo
发明人： Shunpei Yamazaki , Atsuo Isobe , Tetsuji Yamaguchi , Hiromichi Godo
IPC分类号： H01L21/265 , H01L21/336 , H01L21/77 , H01L29/10 , H01L29/786
CPC分类号： H01L27/1214 , H01L21/26586 , H01L27/127 , H01L27/1274 , H01L29/66757 , H01L29/78624
摘要： In the invention, a low concentration impurity region is formed between a channel formation region and a source region or a drain region in a semiconductor layer and covered with a gate electrode layer in a thin film transistor The semiconductor layer is doped obliquely to the surface thereof using the gate electrode layer as a mask to form the low concentration impurity region. The semiconductor layer is formed to have an impurity region including an impurity element for imparting one conductivity which is different from conductivity of the thin film transistor, thereby being able to minutely control the properties of the thin film transistor.
摘要翻译：在本发明中，在半导体层中的沟道形成区域和源极区域或漏极区域之间形成低浓度杂质区域，并且在薄膜晶体管中被栅极电极层覆盖。半导体层倾斜地掺杂在其表面上使用栅极电极层作为掩模形成低浓度杂质区域。半导体层形成为具有包含用于赋予与薄膜晶体管的导电性不同的一种导电性的杂质元素的杂质区域，从而能够精细地控制薄膜晶体管的性质。

10. 发明授权

US08530333B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08530333B2
公开(公告)日：2013-09-10
申请号：US12721298
申请日：2010-03-10
申请人： Atsuo Isobe , Hiromichi Godo , Satoshi Shinohara
发明人： Atsuo Isobe , Hiromichi Godo , Satoshi Shinohara
IPC分类号： H01L21/46
CPC分类号： H01L21/76254 , H01L21/02532 , H01L21/02675 , H01L27/1218 , H01L29/66772
摘要： An object is to provide a semiconductor device which solves a problem that can occur when a substrate having an insulating surface is used. The semiconductor device includes a base substrate having an insulating surface; a conductive layer over the insulating surface; an insulating layer over the conductive layer; a semiconductor layer having a channel formation region, a first impurity region, a second impurity region, and a third impurity region provided between the channel formation region and the second impurity region over the insulating layer; a gate insulating layer configured to cover the semiconductor layer; a gate electrode over the gate insulating layer; a first electrode electrically connected to the first impurity region; and a second electrode electrically connected to the second impurity region. The conductive layer is held at a given potential.
摘要翻译：本发明的目的是提供一种半导体器件，其解决了当使用具有绝缘表面的衬底时可能发生的问题。半导体器件包括具有绝缘表面的基底衬底; 绝缘表面上的导电层; 导电层上的绝缘层; 绝缘层上设置有沟道形成区域和第二杂质区域之间的具有沟道形成区域，第一杂质区域，第二杂质区域和第三杂质区域的半导体层; 构造成覆盖半导体层的栅极绝缘层; 栅绝缘层上的栅电极; 电连接到第一杂质区的第一电极; 和与第二杂质区电连接的第二电极。导电层保持在给定的电位。

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