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1. 发明授权

US4945517A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US4945517A
公开(公告)日：1990-07-31
申请号：US184256
申请日：1988-04-21
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Hiroyuki Yamasaki , Konishi Yasuhiro , Yuto Ikeda
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Hiroyuki Yamasaki , Konishi Yasuhiro , Yuto Ikeda
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4076 , G11C11/417 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4076
摘要： A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal W having a shorter duration than that of the signal W at a down edge of the signal W as a trigger. The output signal W of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.
摘要翻译：提供了在写周期期间变为不活动的I / O负载（5）的半导体动态RAM包括用于接收读/写指示信号和上行和下拉以指示从存储单元读取和写入数据的单稳态多谐振荡器（16） 2），并输出信号和上行和下拉沿W信号和上行和下拉沿W信号和上升沿和W的持续时间W作为触发。单稳态多谐振荡器（16）的输出信号和上升沿W被提供为用于使I / O负载（5）无效的控制信号。

2. 发明授权

US5079748A Dynamic random access memory with read-write signal of shortened duration 失效
标题翻译：动态随机访问存储器，具有读写信号的短时间
公开(公告)号：US5079748A
公开(公告)日：1992-01-07
申请号：US469125
申请日：1990-01-24
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Hiroyuki Yamasaki , Yasuhiro Konishi , Yuto Ikeda
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Hiroyuki Yamasaki , Yasuhiro Konishi , Yuto Ikeda
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4076 , G11C11/417 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4076
摘要： A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

3. 发明授权

US4837747A Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block 失效
标题翻译：冗余电路具有响应于选定单元块中的有缺陷单元的地址的备用主译码器
公开(公告)号：US4837747A
公开(公告)日：1989-06-06
申请号：US126349
申请日：1987-11-30
申请人： Katsumi Dosaka , Masaki Kumanoya , Hideshi Miyatake , Hideto Hidaka , Yasuhiro Konishi , Hiroyuki Yamasaki , Yuto Ikeda , Kazuhiro Tsukamoto , Masaki Shimoda
发明人： Katsumi Dosaka , Masaki Kumanoya , Hideshi Miyatake , Hideto Hidaka , Yasuhiro Konishi , Hiroyuki Yamasaki , Yuto Ikeda , Kazuhiro Tsukamoto , Masaki Shimoda
IPC分类号： G11C8/12 , G11C29/00
CPC分类号： G11C29/806 , G11C8/12
摘要： A memory cell array is divided into four blocks #1 to #4. The blocks #1 and #3 are operated when a row address signal RA.sub.8 equals "0". The blocks #2 and #4 are operated when the row address signal RA.sub.8 equals "1". A spare row sub-decoder is provided in each of the blocks. Spare row sub-decoders in the blocks #1 and #2 are connected to a spare row main decoder through a single spare decoder selecting line. The spare row sub-decoders in the blocks #2 and #4 are connected to the other spare row main decoder through another spare decoder selecting line. The spare main decoders are responsive to the row address signal RA.sub.8 and row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7 for operating a spare row sub-decoder in a block which is in the operating state.
摘要翻译：存储单元阵列被分成四个块＃1到＃4。当行地址信号RA8等于“0”时，块＃1和＃3被操作。当行地址信号RA8等于“1”时，块＃2和＃4被操作。在每个块中提供备用行子解码器。块＃1和＃2中的备用行子解码器通过单个备用解码器选择线连接到备用主主解码器。块＃2和＃4中的备用行子解码器通过另一个备用解码器选择线连接到另一备用行主解码器。备用主解码器响应于行地址信号RA8和行地址信号RA2，RA2。。。，RA7，RA7，用于在处于操作状态的块中操作备用行子解码器。

4. 发明授权

US4843596A Semiconductor memory device with address transition detection and timing control 失效
标题翻译：具有地址转换检测和定时控制的半导体存储器件
公开(公告)号：US4843596A
公开(公告)日：1989-06-27
申请号：US124554
申请日：1987-11-24
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C8/18
CPC分类号： G11C8/18 , G11C7/22
摘要： A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.
摘要翻译：一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

5. 发明授权

US4823322A Dynamic random access memory device having an improved timing arrangement 失效
标题翻译：具有改进的定时布置的动态随机存取存储器件
公开(公告)号：US4823322A
公开(公告)日：1989-04-18
申请号：US102683
申请日：1987-09-30
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
IPC分类号： G11C11/407 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/413 , G11C7/00
CPC分类号： G11C11/4076
摘要： A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.
摘要翻译：具有连接在一对输入/输出线之间的输入/输出负载和用于产生内部/ RAS信号的动态随机存取存储器件，该内部/ RAS信号具有相对于外部/ RAS信号的相同转变延迟的复位转变。内部/ RAS信号至少控制施加到所选择的存储单元的晶体管的字信号和施加到使能晶体管的使能信号，从而使存储器单元和使能晶体管变为不导通的时间被延迟相对于连接在每对位线和输入/输出线之间的传输晶体管的时间变得不导通。

6. 发明授权

US06064608A Semiconductor memory device and methods for inspecting and manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06064608A
公开(公告)日：2000-05-16
申请号：US227572
申请日：1999-01-08
申请人： Yuto Ikeda
发明人： Yuto Ikeda
IPC分类号： G01R31/28 , G11C29/02 , G11C29/12 , G11C7/00
CPC分类号： G11C29/02
摘要： A semiconductor memory device comprising a plurality of word lines that come in two types: ordinary word lines planned to be used ordinarily, and redundant word lines to be used to replace any ordinary word line judged faulty. Boosting transistors are incorporated to boost all bit lines forcibly to a supply voltage. When the bit lines are brought to the supply voltage while the word lines are connected to ground, a memory cell may be found written with data represented by the supply voltage on the bit lines. This reveals a short-circuit between a bit line and the word line corresponding to the memory cell. The short-circuited word line is then replaced by a redundant word line.
摘要翻译：一种包括多个字线的半导体存储器件，它们分为两种类型：一般计划使用的普通字线，以及用于替代任何被判断为错误的普通字线的冗余字线。引入升压晶体管将所有位线强制提升为电源电压。当字线连接到地线时，当位线被带到电源电压时，可以发现用位线上的电源电压表示的数据写入存储单元。这显示了位线和对应于存储单元的字线之间的短路。短路字线由冗余字线代替。

7. 发明授权

US4734889A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4734889A
公开(公告)日：1988-03-29
申请号：US837359
申请日：1986-03-06
申请人： Koichiro Mashiko , Yoshikazu Morooka , Tadato Yamagata , Yuto Ikeda
发明人： Koichiro Mashiko , Yoshikazu Morooka , Tadato Yamagata , Yuto Ikeda
IPC分类号： G11C11/408 , G11C29/00 , G11C13/00 , G11C11/40
CPC分类号： G11C29/84
摘要： A spare Y decoder is provided with MOS transistors 14 and 20 for charge on both sides of a parasitic resistor 19. As a result, nodes N1 and N2 are rapidly charged by the MOS transistors 20 and 14 for charge, respectively.
摘要翻译：备用Y解码器设置有MOS晶体管14和20，用于在寄生电阻器19的两侧充电。结果，节点N1和N2分别被MOS晶体管20和14快速充电。

8. 发明授权

US5243574A Shared sense amplifier type semiconductor memory device 失效
标题翻译：共享信号放大器类型半导体存储器件
公开(公告)号：US5243574A
公开(公告)日：1993-09-07
申请号：US794269
申请日：1991-11-19
申请人： Yuto Ikeda
发明人： Yuto Ikeda
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4076 , G11C11/4091
CPC分类号： G11C11/4076 , G11C11/4091
摘要： A semiconductor memory device with two memory cell arrays. Memory cell arrays are commonly provided with a group of sense amplifiers. Each sense amplifier of a group of sense amplifiers is connected to a corresponding bit line pair within one memory cell array through a transmission transistor pair formed of N channel MOS transistors, and connected to a corresponding bit line pair within the other memory cell array through a transmission transistor pair formed of P channel MOS transistors. The same control signals are applied to gates of these transmission transistor pairs. The control signals maintain 1/2.multidot.Vcc level during a precharge period, and rise to high levels or fall down to low levels.
摘要翻译：具有两个存储单元阵列的半导体存储器件。存储单元阵列通常配置有一组读出放大器。一组读出放大器的每个读出放大器通过由N沟道MOS晶体管形成的透射晶体管对连接到一个存储单元阵列内的对应的位线对，并且通过一个存储单元阵列中的相应的位线对连接到另一个存储单元阵列中传输晶体管对由P沟道MOS晶体管构成。相同的控制信号施加到这些传输晶体管对的栅极。控制信号在预充电期间保持1 / 2xVcc电平，并升高到高电平或降至低电平。

9. 发明申请

US20080235541A1 METHOD FOR TESTING A WORD LINE FAILURE 审中-公开
标题翻译：测试字线故障的方法
公开(公告)号：US20080235541A1
公开(公告)日：2008-09-25
申请号：US11688240
申请日：2007-03-19
申请人： Yuto Ikeda
发明人： Yuto Ikeda
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A method for testing a word line failure of a memory device is provided. The memory device comprises a memory cell with a transistor connecting to a word line and a bit line. The method comprises driving the word line to a predetermined voltage level by a word line driver so as to turn off or on the transistor of the memory cell; and reducing the driving ability of the word line drive.
摘要翻译：提供了一种用于测试存储器件的字线故障的方法。存储器件包括具有连接到字线和位线的晶体管的存储单元。该方法包括通过字线驱动器将字线驱动到预定电压电平，以便关闭或者关闭存储器单元的晶体管; 并降低字线驱动的驾驶能力。

10. 发明授权

US06185141B2 Semiconductor device allowing efficient evaluation of fast operation 失效
标题翻译：半导体器件允许有效评估快速操作
公开(公告)号：US06185141B2
公开(公告)日：2001-02-06
申请号：US09572503
申请日：2000-05-18
申请人： Tetsushi Hoshita , Yuto Ikeda
发明人： Tetsushi Hoshita , Yuto Ikeda
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C7/12 , G11C11/401 , G11C29/50 , G11C29/50012
摘要： A precharge control circuit controls on/off of transfer gates to set a signal level of a precharge control signal in accordance with a level of a control signal input to a precharge command input pad when a write recovery test signal is active. In a normal operation, the precharge control circuit deactivates the write recovery test signal to set the signal level of the precharge control signal in accordance with a combination of control signals. Consequently, the precharge operation can be started in accordance with an arbitrary control signal generated by an external memory tester or the like in a test mode, and thereby evaluation of a write recovery time can be executed.
摘要翻译：当写入恢复测试信号有效时，预充电控制电路根据输入到预充电命令输入板的控制信号的电平来控制传输门的导通/关断，以设定预充电控制信号的信号电平。在正常操作中，预充电控制电路取消对写恢复测试信号的去激活，以根据控制信号的组合设置预充电控制信号的信号电平。因此，可以根据在测试模式中由外部存储器测试仪等产生的任意控制信号来开始预充电操作，从而可以执行写恢复时间的评估。

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