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1. 发明授权

US06718426B2 Cache memory apparatus and central processor, hand-held device and arithmetic processor using the same 失效
标题翻译：高速缓存存储器和中央处理器，手持设备和使用其的算术处理器
公开(公告)号：US06718426B2
公开(公告)日：2004-04-06
申请号：US09791855
申请日：2001-02-26
申请人： Hidemitsu Naya , Hideyuki Okamoto , Koji Kawaki , Yuji Sugaya , Yuichiro Morita , Yoshitaka Takahashi
发明人： Hidemitsu Naya , Hideyuki Okamoto , Koji Kawaki , Yuji Sugaya , Yuichiro Morita , Yoshitaka Takahashi
IPC分类号： G06F1200
CPC分类号： G06F9/3802 , G06F12/0848
摘要： A cache memory apparatus is provided with a cache memory for storing thereinto at least one of information about an instruction group related to a system control and information about a data group, an address managment table for managing both an address and a range with respect to the cache memory into which the information is stored, and a selection circuit for selecting the cache memory in response to an access to the address management table. As a result, information related to a system control is stored into the cache memory apparatus.
摘要翻译：高速缓冲存储器装置具有高速缓冲存储器，用于存储关于与系统控制相关的指令组和关于数据组的信息的信息中的至少一个，用于管理地址和范围的地址管理表缓存存储器，其中存储有信息;以及选择电路，用于响应于访问地址管理表而选择高速缓冲存储器。结果，与系统控制相关的信息被存储到高速缓冲存储器装置中。

2. 发明授权

US06205517B1 Main memory control apparatus for use in a memory having non-cacheable address space allocated to DMA accesses 失效
标题翻译：主存储器控制装置，用于具有分配给DMA访问的不可缓存地址空间的存储器
公开(公告)号：US06205517B1
公开(公告)日：2001-03-20
申请号：US08832256
申请日：1997-04-03
申请人： Yuji Sugaya
发明人： Yuji Sugaya
IPC分类号： G06F1208
CPC分类号： G06F12/0848 , G06F12/0888
摘要： A CPU and a DMA device employ in common an address area from which data cannot be loaded into a cache memory. A read buffer memory and a write buffer memory loading therein data read from and written into that address area are provided. In read access from the CPU or DMA device to the common address area, if data to be accessed exists in any buffer memory, the data in the buffer memory is transferred to the CPU or DMA device. If data to be accessed does not exist in any buffer memory, data at addresses different from the read access address from the CPU or DMA device only in lower bits of fixed length is read from the main memory unit and then loaded into the buffer memory after performing data error checking and correcting of the read data.
摘要翻译： CPU和DMA设备共同地使用数据不能被加载到高速缓冲存储器的地址区域。提供读取缓冲存储器和写入缓冲存储器，其中加载从该地址区读取并写入该地址区域的数据。在从CPU或DMA设备到公共地址区域的读取访问中，如果要访问的数据存在于任何缓冲存储器中，则将缓冲存储器中的数据传输到CPU或DMA设备。如果要访问的数据不存在于任何缓冲存储器中，则从主存储器单元读取从主存储器单元读取与来自CPU或DMA器件的读访问地址不同的数据，然后将其从该存储器单元中加载到缓冲存储器中执行读取数据的数据错误检查和校正。

3. 发明授权

US5551789A Cosmetic material container 失效
标题翻译：化妆品容器
公开(公告)号：US5551789A
公开(公告)日：1996-09-03
申请号：US317549
申请日：1994-10-04
申请人： Akira Okawa , Yuji Sugaya
发明人： Akira Okawa , Yuji Sugaya
IPC分类号： A45D34/04 , B43K8/08 , B43K8/04 , B43K9/00
CPC分类号： B43K8/08 , A45D34/042 , A45D2200/1018
摘要： A cosmetic material container comprises: a sleeve holder 1 having an open front end 12 and an open rear end 11; a tail plug 2 for closing the open rear end 11 of the sleeve holder 1; an applying tip unit 3 secured to an open front end side of the sleeve holder 1; and a double cap unit 4 attachably and detachably coupled to the sleeve holder 1 on the outer periphery of its front end 12, the applying tip unit 3 including an adjuster 31 provided on its outer periphery with annular grooves 311, a porous joining core 32 inserted into an axial hole 312 in the adjuster 31 and communicating with a part of the annular grooves 31, and a porous tip 33 connected to a front end of the joining core 32 and inserted in a socket 313 provided in a front end of the adjuster 31, a cosmetic material reservoir 13 being defined between a rear end of the adjuster 31 and the tail end 2 in the sleeve holder 1, and the porous joining core 32 being disposed in the adjuster 31 to project its rear end in the reservoir 13.
摘要翻译：化妆品容器包括：具有敞开的前端12和敞开的后端11的套筒保持器1; 用于封闭套筒保持器1的打开的后端11的尾塞2; 固定在套筒保持架1的敞开的前端侧的涂抹头单元3; 以及双头盖单元4，该双盖单元4在其前端12的外周上可连接地可拆卸地联接到套筒保持器1，该施加尖端单元3包括在其外周上设置有环形槽311的调节器31，插入的多孔接合芯32 调节器31中的轴向孔312并与环形槽31的一部分连通，并且连接到接合芯32的前端并插入设置在调节器31的前端的插座313中的多孔端头33 在调节器31的后端和套筒保持器1中的尾端2之间限定了化妆品贮存器13，并且多孔接合芯32设置在调节器31中，以将其后端突出到储存器13中。

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