专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07387481B2 Cargo box outer hook mounting structure 有权
标题翻译：货箱外钩安装结构
公开(公告)号：US07387481B2
公开(公告)日：2008-06-17
申请号：US11153605
申请日：2005-06-16
申请人： Hidekazu Suzuki , Yoshihisa Kojima
发明人： Hidekazu Suzuki , Yoshihisa Kojima
IPC分类号： B60P7/08
CPC分类号： B60P7/0807
摘要： An outer hook mounting structure for a cargo box, comprising: a side panel formed by an outer panel and an inner panel extending in a longitudinal direction of a vehicle on a side of the cargo box; a reinforcement disposed between the outer panel and the inner panel and fixed to the inner panel; passage holes provided in correspondence with the outer panel, the reinforcement, and the inner panel; and an outer hook passing through the outer panel and having an end portion fixed to the reinforcement.
摘要翻译：一种用于货物箱的外钩安装结构，包括：一个侧板，由一个外板和一个在货箱的一侧沿车辆纵向方向延伸的内板形成; 加强件，设置在所述外板和所述内板之间并固定到所述内板; 与外板，加强件和内板相对设置的通孔; 以及穿过外板并具有固定到加强件的端部的外钩。

2. 发明申请

US20050280271A1 Cargo box outer hook mounting structure 有权
标题翻译：货箱外钩安装结构
公开(公告)号：US20050280271A1
公开(公告)日：2005-12-22
申请号：US11153605
申请日：2005-06-16
申请人： Hidekazu Suzuki , Yoshihisa Kojima
发明人： Hidekazu Suzuki , Yoshihisa Kojima
IPC分类号： B60P7/06 , B60P7/08
CPC分类号： B60P7/0807
摘要： An outer hook mounting structure for a cargo box, comprising: a side panel formed by an outer panel and an inner panel extending in a longitudinal direction of a vehicle on a side of the cargo box; a reinforcement disposed between the outer panel and the inner panel and fixed to the inner panel; passage holes provided in correspondence with the outer panel, the reinforcement, and the inner panel; and an outer hook passing through the outer panel and having an end portion fixed to the reinforcement.
摘要翻译：一种用于货物箱的外钩安装结构，包括：一个侧板，由一个外板和一个在货箱的一侧沿车辆纵向延伸的内板形成; 加强件，设置在所述外板和所述内板之间并固定到所述内板; 与外板，加强件和内板相对设置的通孔; 以及穿过外板并具有固定到加强件的端部的外钩。

3. 发明授权

US07216312B2 Determining one or more reachable states in a circuit using distributed computing and one or more partitioned data structures 失效
标题翻译：使用分布式计算和一个或多个分区数据结构确定电路中的一个或多个可达状态
公开(公告)号：US07216312B2
公开(公告)日：2007-05-08
申请号：US10704234
申请日：2003-11-07
申请人： Jawahar Jain , Amit Narayan , Yoshihisa Kojima , Takaya Ogawa , Subramanian K. Iyer , Debashis Sahoo
发明人： Jawahar Jain , Amit Narayan , Yoshihisa Kojima , Takaya Ogawa , Subramanian K. Iyer , Debashis Sahoo
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one embodiment, a method for determining one or more reachable states in a circuit using distributed computing and one or more partitioned data structures includes, at a first one of multiple computing systems, receiving a first partition of a circuit. The first partition corresponds to a first binary decision diagram (BDD) having a first density. The method includes performing a first reachability analysis on the first partition using the first BDD until a fixed point in the first partition has been reached and, if, during the first reachability analysis, the size of the first BDD exceeds a threshold, discarding the first BDD. The method includes communicating with at least one second one of the multiple computing systems. The second one of the multiple computing systems has received a second partition of the circuit. The second one of the multiple computing systems has performed a second reachability analysis on the second BDD without discarding the second BDD.
摘要翻译：在一个实施例中，用于使用分布式计算和一个或多个分区数据结构来确定电路中的一个或多个可达状态的方法包括在多个计算系统中的第一个处接收电路的第一分区。第一分区对应于具有第一密度的第一二进制决策图（BDD）。该方法包括使用第一BDD对第一分区执行第一可达性分析，直到达到第一分区中的固定点，并且如果在第一可达性分析期间第一BDD的大小超过阈值，则丢弃第一 BDD。该方法包括与多个计算系统中的至少一个第二个通信。多个计算系统中的第二个已经接收到电路的第二分区。多个计算系统中的第二个对第二BDD进行了第二次可达性分析，而不丢弃第二个BDD。

4. 发明授权

US07941776B2 Method of IC design optimization via creation of design-specific cells from post-layout patterns 有权
标题翻译：通过从后布局模式创建设计特定单元的IC设计优化方法
公开(公告)号：US07941776B2
公开(公告)日：2011-05-10
申请号：US11805947
申请日：2007-05-25
申请人： Purnabha Majumder , Balakrishna Kumthekar , Nimish Rameshbhai Shah , John Mowchenko , Pramit Anikumar Chavda , Yoshihisa Kojima , Hiroaki Yoshida , Vamsi Boppana
发明人： Purnabha Majumder , Balakrishna Kumthekar , Nimish Rameshbhai Shah , John Mowchenko , Pramit Anikumar Chavda , Yoshihisa Kojima , Hiroaki Yoshida , Vamsi Boppana
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power, noise, etc.), which will be then implemented as a standard cell (also known hereafter as metacell), from a set of post-layout patterns. A post-layout pattern represents a part or whole of a standard cell and contains information regarding the pattern including, but not limited to, layout, timing, area, power and noise. As the metacells are created from post-layout patterns, the inaccuracies of prior dynamic library techniques are easily avoided. Such metacells, being design-specific, are optimized to satisfy the constraints imposed by the design context, thus bringing the powerful design-specific customization to standard cell-based design methodology.
摘要翻译：通过自动或手动创建具有期望特性（例如，性能，面积，功率，噪声等）的设计特定单元的闭环IC设计优化过程，其将被实现为标准单元（以下也称为metacell ），从一组后布局模式。后置布局图案表示标准单元的一部分或全部，并且包含关于图案的信息，包括但不限于布局，定时，面积，功率和噪声。由于电池是从后期布局模式创建的，所以很容易避免先前的动态库技术的不准确之处。针对特定设计的这种电池进行了优化，以满足设计上下文所施加的限制，从而将强大的设计特定定制功能带入标准的基于单元格的设计方法。

5. 发明申请

US20080127000A1 Method of IC design optimization via creation of design-specific cells from post-layout patterns 有权
标题翻译：通过从后布局模式创建设计特定单元的IC设计优化方法
公开(公告)号：US20080127000A1
公开(公告)日：2008-05-29
申请号：US11805947
申请日：2007-05-25
申请人： Purnabha Majumder , Balakrishna Kumthekar , Nimish Rameshbhai Shah , John Mowchenko , Pramit Anikumar Chavda , Yoshihisa Kojima , Hiroaki Yoshida , Vamsi Boppana
发明人： Purnabha Majumder , Balakrishna Kumthekar , Nimish Rameshbhai Shah , John Mowchenko , Pramit Anikumar Chavda , Yoshihisa Kojima , Hiroaki Yoshida , Vamsi Boppana
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power, noise, etc.), which will be then implemented as a standard cell (also known hereafter as metacell), from a set of post-layout patterns. A post-layout pattern represents a part or whole of a standard cell and contains information regarding the pattern including, but not limited to, layout, timing, area, power and noise. As the metacells are created from post-layout patterns, the inaccuracies of prior dynamic library techniques are easily avoided. Such metacells, being design-specific, are optimized to satisfy the constraints imposed by the design context, thus bringing the powerful design-specific customization to standard cell-based design methodology.
摘要翻译：通过自动或手动创建具有期望特性（例如，性能，面积，功率，噪声等）的设计特定单元的闭环IC设计优化过程，其将被实现为标准单元（以下也称为metacell ），从一组后布局模式。后置布局图案表示标准单元的一部分或全部，并且包含关于图案的信息，包括但不限于布局，定时，面积，功率和噪声。由于电池是从后期布局模式创建的，所以很容易避免先前的动态库技术的不准确之处。针对特定设计的这种电池进行了优化，以满足设计上下文所施加的限制，从而将强大的设计特定定制功能带入标准的基于单元格的设计方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式