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1. 发明授权

US06380036B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06380036B1
公开(公告)日：2002-04-30
申请号：US09694003
申请日：2000-10-23
申请人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
发明人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
IPC分类号： H01L21336
CPC分类号： H01L21/26506 , H01L29/1033 , H01L29/105 , H01L29/66575
摘要： A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.
摘要翻译：在硅衬底的表面上形成硼扩散区。在硼扩散区的表面形成一对n型源/漏区。在位于成对的源/漏区之间的区域之间形成有栅极电极，其间具有栅极绝缘膜。在位于成对的n型源极/漏极区之间的硅衬底的表面处形成氮注入区。氮注入区域在硅衬底表面的深度不超过500的位置具有峰值氮浓度。由此，可以获得容易小型化的晶体管结构。

2. 发明授权

US6153910A Semiconductor device with nitrogen implanted channel region 失效
标题翻译：具有氮注入沟道区的半导体器件
公开(公告)号：US6153910A
公开(公告)日：2000-11-28
申请号：US940400
申请日：1997-10-01
申请人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
发明人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/772 , H01L29/76
CPC分类号： H01L21/26506 , H01L29/1033 , H01L29/105 , H01L29/66575
摘要： A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.
摘要翻译：在硅衬底的表面上形成硼扩散区。在硼扩散区的表面形成一对n型源/漏区。在位于成对的源/漏区之间的区域之间形成有栅极电极，其间具有栅极绝缘膜。在位于成对的n型源极/漏极区之间的硅衬底的表面处形成氮注入区。氮注入区域在硅衬底表面的深度不超过500的位置具有峰值氮浓度。由此，可以获得容易小型化的晶体管结构。

3. 发明授权

US5557129A Semiconductor MOSFET device having a shallow nitrogen implanted channel region 失效
标题翻译：具有浅氮注入沟道区的半导体MOSFET器件
公开(公告)号：US5557129A
公开(公告)日：1996-09-17
申请号：US452611
申请日：1995-05-25
申请人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
发明人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/10 , H01L31/062
CPC分类号： H01L29/66575 , H01L21/26506 , H01L29/1033 , H01L29/105
摘要： A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.
摘要翻译：在硅衬底的表面上形成硼扩散区。在硼扩散区的表面形成一对n型源/漏区。在位于成对的源/漏区之间的区域之间形成有栅极电极，其间具有栅极绝缘膜。在位于成对的n型源极/漏极区之间的硅衬底的表面处形成氮注入区。氮注入区域在硅衬底表面的深度不超过500的位置具有峰值氮浓度。由此，可以获得容易小型化的晶体管结构。

4. 发明授权

US5550409A Semiconductor device having internal wire and method of fabricating the same 失效
标题翻译：具有内部电线的半导体器件及其制造方法
公开(公告)号：US5550409A
公开(公告)日：1996-08-27
申请号：US339662
申请日：1994-11-14
申请人： Takehisa Yamaguchi , Hidekazu Oda
发明人： Takehisa Yamaguchi , Hidekazu Oda
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8244 , H01L23/52 , H01L23/522 , H01L23/532 , H01L27/11 , H01L23/48 , H01L29/40
CPC分类号： H01L27/1112 , H01L23/53257 , H01L27/11 , H01L2924/0002
摘要： In order to obtain a semiconductor device having an internal wire of low resistance, a conductive layer whose surface is silicified is provided in a surface of a semiconductor substrate. A conductor whose surface is silicified is provided on the semiconductor substrate in proximity to the conductive layer. This semiconductor device is provided with an internal wiring layer, which is formed by a titanium film and a titanium silicide layer for electrically connecting the surface of the conductive layer and a surface of an end of the conductor with each other, to cover a side wall surface and a bottom surface of a contact hole.
摘要翻译：为了获得具有低电阻的内部线的半导体器件，其表面被硅化的导电层设置在半导体衬底的表面中。其表面被硅化的导体设置在半导体衬底附近的导电层上。该半导体器件设置有内部布线层，其由钛膜和钛硅化物层形成，用于将导电层的表面和导体的端部的表面彼此电连接以覆盖侧壁表面和接触孔的底面。

5. 发明授权

US5837606A Semiconductor device having internal wire and method of fabricating the same 失效
公开(公告)号：US5837606A
公开(公告)日：1998-11-17
申请号：US668012
申请日：1996-06-17
申请人： Takehisa Yamaguchi , Hidekazu Oda
发明人： Takehisa Yamaguchi , Hidekazu Oda
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8244 , H01L23/52 , H01L23/522 , H01L23/532 , H01L27/11 , H01L21/4763
CPC分类号： H01L27/1112 , H01L23/53257 , H01L27/11 , H01L2924/0002
摘要： In order to obtain a semiconductor device having an internal wire of low resistance, a conductive layer whose surface is silicified is provided in a surface of a semiconductor substrate. A conductor whose surface is silicified is provided on the semiconductor substrate in proximity to the conductive layer. This semiconductor device is provided with an internal wiring layer, which is formed by a titanium film and a titanium silicide layer for electrically connecting the surface of the conductive layer and a surface of an end of the conductor with each other, to cover a side wall surface and a bottom surface of a contact hole.

6. 发明授权

US5218217A Dynamic random access memory device and method of manufacturing 失效
标题翻译：动态随机存取存储器件及其制造方法
公开(公告)号：US5218217A
公开(公告)日：1993-06-08
申请号：US568567
申请日：1990-08-16
申请人： Hidekazu Oda , Kiyoteru Kobayashi , Takehisa Yamaguchi
发明人： Hidekazu Oda , Kiyoteru Kobayashi , Takehisa Yamaguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/786
CPC分类号： H01L27/10802 , H01L27/10805 , H01L29/78654
摘要： Each memory cell of a dynamic random access memory comprises a semiconductor layer of a first conductivity type, one and the other impurity regions of a second conductivity type, a gate electrode, a capacitor impurity region of the first conductivity type, and a capacitor electrode. The semiconductor layer of the first conductivity type comprises a first surface and a second surface located opposite to the first surface. One and the other impurity regions are formed spaced apart from each other in the semiconductor layer so as to define a channel region with a channel surface being a part of the first surface of the semiconductor layer. The gate electrode is formed on the channel surface through a gate insulating film. The capacitor impurity region is formed opposing to the channel region, near the second surface of the semiconductor layer and having a concentration higher than that of the semiconductor layer. The capacitor electrode is formed on the capacitor impurity region through a dielectric film. Reduced surface area occupied by each memory cell comprising a field effect transistor and a capacitor enables miniaturization of the memory cell. Electric charges generated by the impact ionization phenomenon are stored in the capacitor, so that a power consumed in a writing operation of data can be reduced.
摘要翻译：动态随机存取存储器的每个存储单元包括第一导电类型的半导体层，第二导电类型的一个和另一个杂质区，第一导电类型的栅电极，电容器杂质区和电容器电极。第一导电类型的半导体层包括第一表面和与第一表面相对的第二表面。在半导体层中形成彼此间隔开的一个和其它杂质区，以便限定沟道区，其中沟道表面是半导体层的第一表面的一部分。栅电极通过栅极绝缘膜形成在沟道表面上。在半导体层的第二表面附近形成与沟道区相对的电容器杂质区，其浓度高于半导体层的浓度。电容器电极通过电介质膜形成在电容器杂质区上。由包括场效应晶体管和电容器的每个存储单元占用的减小的表面积使得能够使存储单元小型化。由电击现象产生的电荷存储在电容器中，从而可以减少数据写入操作中消耗的功率。

7. 发明授权

US5270242A Method for fabricatins dynamic random access memory device having a capacitor for storing impact ionization charges 失效
标题翻译：一种用于制造具有用于存储冲击电离电荷的电容器的动态随机存取存储器件的方法
公开(公告)号：US5270242A
公开(公告)日：1993-12-14
申请号：US17903
申请日：1993-02-16
申请人： Hidekazu Oda , Kiyoteru Kobayashi , Takehisa Yamaguchi
发明人： Hidekazu Oda , Kiyoteru Kobayashi , Takehisa Yamaguchi
IPC分类号： H01L27/108 , H01L29/786 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10805 , H01L29/78654
摘要： Each memory cell of a dynamic random access memory comprises a semiconductor layer of a first conductivity type, one and the other impurity regions of a second conductivity type, a gate electrode, a capacitor impurity region of the first conductivity type, and a capacitor electrode. The semiconductor layer of the first conductivity type comprises a first surface and a second surface located opposite to the first surface. One and the other impurity regions are formed spaced apart from each other in the semiconductor layer so as to define a channel region with a channel surface being a part of the first surface of the semiconductor layer. The gate electrode is formed on the channel surface through a gate insulating film. The capacitor impurity region is formed opposing to the channel region, near the second surface of the semiconductor layer and having a concentration higher than that of the semiconductor layer. The capacitor electrode is formed on the capacitor impurity region through a dielectric film. Reduced surface area occupied by each memory cell comprising a field effect transistor and a capacitor enables miniaturization of the memory cell. Electric charges generated by the impact ionization phenomenon are stored in the capacitor, so that a power consumed in a writing operation of data can be reduced.
摘要翻译：动态随机存取存储器的每个存储单元包括第一导电类型的半导体层，第二导电类型的一个和另一个杂质区，第一导电类型的栅电极，电容器杂质区和电容器电极。第一导电类型的半导体层包括第一表面和与第一表面相对的第二表面。在半导体层中形成彼此间隔开的一个和其它杂质区，以便限定沟道区，其中沟道表面是半导体层的第一表面的一部分。栅电极通过栅极绝缘膜形成在沟道表面上。在半导体层的第二表面附近形成与沟道区相对的电容器杂质区，其浓度高于半导体层的浓度。电容器电极通过电介质膜形成在电容器杂质区上。由包括场效应晶体管和电容器的每个存储单元占用的减小的表面积使得能够使存储单元小型化。由电击现象产生的电荷存储在电容器中，从而可以减少数据写入操作中消耗的功率。

8. 发明授权

US06475844B1 Field effect transistor and method of manufacturing same 失效
标题翻译：场效应晶体管及其制造方法相同
公开(公告)号：US06475844B1
公开(公告)日：2002-11-05
申请号：US09629485
申请日：2000-07-31
申请人： Hidekazu Oda , Tomohiro Yamashita , Shuichi Ueno
发明人： Hidekazu Oda , Tomohiro Yamashita , Shuichi Ueno
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L21/28518 , H01L27/10873 , H01L27/10888 , H01L27/10894 , H01L29/4983 , H01L29/66659
摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.
摘要翻译：当扩散区域（7a）连接到位线并且扩散区域（8a）连接到栅极电极（3a）的远离存储节点的表面的一部分中时，形成硅化区域（11a）存储节点。在与位线连接的扩散区域（7a）的表面形成硅化区域（12a）。提供一种MOSFET，其抑制从存储节点到栅电极的漏电流并且降低连接到位线的扩散区域的电阻和所述栅电极的电阻。

9. 发明授权

US06300664B1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06300664B1
公开(公告)日：2001-10-09
申请号：US08880508
申请日：1997-06-23
申请人： Takashi Kuroi , Shuichi Ueno , Hidekazu Oda , Satoshi Shimizu
发明人： Takashi Kuroi , Shuichi Ueno , Hidekazu Oda , Satoshi Shimizu
IPC分类号： H01L2976
CPC分类号： H01L29/0847 , H01L21/28176 , H01L21/28202 , H01L21/823857 , H01L29/4908 , H01L29/4916 , H01L29/4933 , H01L29/51 , H01L29/518 , H01L29/665 , H01L29/66575 , H01L29/6659 , H01L29/66765 , H01L29/7833 , H01L29/78618
摘要： Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.
摘要翻译：获得的是能够防止栅电极中所含杂质扩散的半导体器件及其制造方法。在该半导体器件中，形成在P型硅衬底上的栅极氧化膜和P +型栅极掺杂有氮。

10. 发明授权

US6130463A Field effect transistor and method of manufacturing same 有权
公开(公告)号：US6130463A
公开(公告)日：2000-10-10
申请号：US346999
申请日：1999-07-02
申请人： Hidekazu Oda , Tomohiro Yamashita , Shuichi Ueno
发明人： Hidekazu Oda , Tomohiro Yamashita , Shuichi Ueno
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/49 , H01L21/441
CPC分类号： H01L27/10852 , H01L21/28518 , H01L27/10894 , H01L29/4983 , H01L29/66659 , H01L27/10873 , H01L27/10888
摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

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