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    • 4. 发明授权
    • Image processing apparatus and method, computer program, and storage medium
    • 图像处理装置和方法,计算机程序和存储介质
    • US07127115B2
    • 2006-10-24
    • US10393069
    • 2003-03-21
    • Hidefumi OsawaTadayoshi NakayamaKen-ichi OhtaShinichi KatoNaoki Ito
    • Hidefumi OsawaTadayoshi NakayamaKen-ichi OhtaShinichi KatoNaoki Ito
    • G06K9/36G06K9/46
    • G06T9/005
    • The present invention allows an image to be coded within a target size without necessitating the image to be input again during the coding of the image, with a mode reflecting a user's intention for coding. To solve this problem, input image data is coded at coding unit 102 and stored into first and second memories, respectively. Coding sequence unit 108 monitors the quantity of codes. When a set value is determined to be reached, coding sequence unit 108 makes data in first memory to be discarded and directs coding means to further increase a quantization step, and continues coding. As previous coded data is stored in second memory, the data is re-coded with the same quantization step as that of coding unit 102 after changing of a parameter at re-coding unit 109, and the re-coded data is stored into first and second memory. At this moment, coding unit 102 and re-coding unit 109 perform an operation and coding on quantization error according to a mode of quantization operation designated at mode designation unit 125.
    • 本发明允许将图像编码在目标尺寸内,而不需要在图像编码期间再次输入图像,其中模式反映用户的编码意图。 为了解决这个问题,输入图像数据被分别编码在编码单元102中并存储到第一和第二存储器中。 编码序列单元108监视代码的数量。 当确定要达到设定值时,编码序列单元108使第一存储器中的数据被丢弃,并指示编码装置进一步增加量化步长,并继续编码。 由于先前的编码数据存储在第二存储器中,所以在重新编码单元109中改变参数之后,以与编码单元102相同的量化级重新编码数据,并将重新编码的数据存储在第一存储器 第二个记忆 此时,编码单元102和重新编码单元109根据在模式指定单元125指定的量化操作的模式来执行对量化误差的操作和编码。
    • 7. 发明授权
    • Data transform apparatus and control method thereof
    • 数据变换装置及其控制方法
    • US07912318B2
    • 2011-03-22
    • US12521204
    • 2008-10-06
    • Tadayoshi Nakayama
    • Tadayoshi Nakayama
    • G06K9/36H04N11/02
    • G06F17/145
    • This invention provides a lossless 4-point Hadamard transform circuit which can minimize the number of times of addition/subtraction calculations, and reduce the number of times of round processing required to convert data including a fractional part into an integer. To this end, a DC coefficient generating unit summates four input data, and shifts the summation result 1 bit to the right to halve the summation result and to round the halved result by truncating a fractional part of the result. This 1-bit shift right result is output as a DC coefficient. An intermediate data generating unit generates, as intermediate value, a difference value between one input data of the four input data and the DC coefficient obtained by the DC coefficient generating unit. An AC coefficient generating unit generates three AC coefficients by adding the intermediate data generated by the intermediate data generating unit to other three input data.
    • 本发明提供了一种无损4点Hadamard变换电路,其可以使加法/减法计算的次数最小化,并减少将包括小数部分的数据转换为整数所需的循环处理次数。 为此,DC系数生成单元将四个输入数据相加,并将求和结果1位向右移动以使求和结果减半,并且通过截断结果的小数部分来舍入该两半的结果。 该1位移位右结果作为直流系数输出。 中间数据生成单元生成四个输入数据的一个输入数据和由DC系数生成单元获得的DC系数之间的差分值作为中间值。 AC系数生成单元通过将由中间数据生成单元生成的中间数据与其他三个输入数据相加来生成3个AC系数。
    • 8. 发明申请
    • DATA TRANSFORM APPARATUS AND CONTROL METHOD THEREOF
    • 数据变换装置及其控制方法
    • US20100104215A1
    • 2010-04-29
    • US12521204
    • 2008-10-06
    • Tadayoshi Nakayama
    • Tadayoshi Nakayama
    • G06K9/36
    • G06F17/145
    • This invention provides a lossless 4-point Hadamard transform circuit which can minimize the number of times of addition/subtraction calculations, and reduce the number of times of round processing required to convert data including a fractional part into an integer. To this end, a DC coefficient generating unit summates four input data, and shifts the summation result 1 bit to the right to halve the summation result and to round the halved result by truncating a fractional part of the result. This 1-bit shift right result is output as a DC coefficient. An intermediate data generating unit generates, as intermediate value, a difference value between one input data of the four input data and the DC coefficient obtained by the DC coefficient generating unit. An AC coefficient generating unit generates three AC coefficients by adding the intermediate data generated by the intermediate data generating unit to other three input data.
    • 本发明提供了一种无损4点Hadamard变换电路,其可以使加法/减法计算的次数最小化,并减少将包括小数部分的数据转换为整数所需的循环处理次数。 为此,DC系数生成单元将四个输入数据相加,并将求和结果1位向右移动以使求和结果减半,并且通过截断结果的小数部分来舍入该两半的结果。 该1位移位右结果作为直流系数输出。 中间数据生成单元生成四个输入数据的一个输入数据和由DC系数生成单元获得的DC系数之间的差分值作为中间值。 AC系数生成单元通过将由中间数据生成单元生成的中间数据与其他三个输入数据相加来生成3个AC系数。
    • 9. 发明授权
    • Image coding apparatus and its control method, and computer program and computer readable storage medium
    • 图像编码装置及其控制方法,以及计算机程序和计算机可读存储介质
    • US07643695B2
    • 2010-01-05
    • US11492812
    • 2006-07-26
    • Tadayoshi Nakayama
    • Tadayoshi Nakayama
    • G06K9/00
    • H04N19/85H04N19/126H04N19/13H04N19/134H04N19/176H04N19/184H04N19/60
    • This invention allows Huffman encoding using a common Huffman table according to basic quantization values Qi,j even when image data expressed by n bits falling within the range from L to K is JPEG-coded, and can suppress the Huffman table size from increasing. To this end, a basic quantization table storage unit stores quantization step values Q0,0 to Q7,7 used in baseline JPEG coding. A minimum quantization step generator outputs a minimum quantization step value Qn—min to a comparator/selector according to the number n of bits of each color component of image data to be coded. The comparator/selector compares the quantization step values Q0,0 to Q7,7 with Qn—min and selects larger ones, and outputs the comparison results to a quantizer as Q′i,j. The quantizer stores Q′i,j in a quantization table storage unit and quantizes orthogonal transformation coefficients output from a DCT transformer.
    • 本发明即使当由L到K的范围内的n位表示的图像数据被JPEG编码时,也可以使用基于基本量化值Qi,j的公共霍夫曼表进行霍夫曼编码,并且可以抑制霍夫曼表的大小增加。 为此,基本量化表存储单元存储在基线JPEG编码中使用的量化步长值Q0,0至Q7,7。 最小量化级发生器根据要编码的图像数据的每个颜色分量的位数n向比较器/选择器输出最小量化步长值Qn-min。 比较器/选择器将量化步长值Q0,0至Q7,7与Qn-min进行比较,并选择较大的值,并将比较结果输出到量化器作为Q'i,j。 量化器将Q'i,j存储在量化表存储单元中,并对从DCT变换器输出的正交变换系数进行量化。
    • 10. 发明申请
    • ENGAGING AND FIXING STRUCTURE AND ENGAGING AND FIXING METHOD
    • 接合和固定结构和接合和固定方法
    • US20090174201A1
    • 2009-07-09
    • US12401886
    • 2009-03-11
    • Tadayoshi Nakayama
    • Tadayoshi Nakayama
    • B60R19/30
    • F16B5/0635B60R13/04B60R2019/525Y10T29/4987Y10T70/5761
    • A bumper is provided with to-be-engaged projections, a radiator grille is provided with engaging projections. The radiator grille is allowed to move and approach bumper rearward of a vehicle. According to this configuration, the engaging projections engage the to-be-engaged projections and they are engaged with and fixed to each other. At this time, a bumper-side seizing unit of the bumper is fitted into a grille-side seizing unit of the radiator grille, thereby limiting the vertical direction. In an engaged state between the engaging projections and the to-be-engaged projections, an inclining surface of one of the engaging projections comes into contact with a rearward inclining surface of the one of the to-be-engaged projections, and an inclining surface of the other engaging projection is separated from a rearward inclining surface of the other to-be-engaged projection.
    • 保险杠设置有待接合的突起,散热器格栅设有接合突起。 散热器格栅被允许移动并接近车辆后方的保险杠。 根据该构造,接合突起与被接合突起接合,并且彼此接合并固定。 此时,保险杠的保险杠侧卡止单元装配在散热器格栅的格栅侧卡住单元中,从而限制了垂直方向。 在接合突起和被接合突起之间的接合状态中,一个接合突起的倾斜表面与被接合突起中的一个的向后倾斜表面接触,并且倾斜表面 的另一个接合突起与另一个待接合突起的向后倾斜表面分离。