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1. 发明申请

US20070064514A1 Control unit and portable terminal 审中-公开
标题翻译：控制单元和便携式终端
公开(公告)号：US20070064514A1
公开(公告)日：2007-03-22
申请号：US11525010
申请日：2006-09-22
申请人： Hideaki Miyamoto , Shigeharu Matsushita , Shinichiro Okada
发明人： Hideaki Miyamoto , Shigeharu Matsushita , Shinichiro Okada
IPC分类号： G11C5/14
CPC分类号： G11C14/00
摘要： A control unit capable of reliably preventing loss of data also when losing power during data processing is obtained. This control unit comprises a volatile memory temporarily storing data used in the control unit and a nonvolatile memory holding data of the volatile memory, for writing the same data as that written in the volatile memory also in the nonvolatile memory upon occurrence of writing in the volatile memory.
摘要翻译：获得能够可靠地防止在数据处理期间失去电力时数据丢失的控制单元。该控制单元包括临时存储在控制单元中使用的数据的易失性存储器和保存易失性存储器的数据的非易失性存储器，用于在写入易失性存储器时写入与易失性存储器中写入的易失性存储器相同的数据记忆。

2. 发明授权

US07933161B2 Memory device configured to refresh memory cells in a power-down state 有权
标题翻译：配置为在掉电状态下刷新存储单元的内存设备
公开(公告)号：US07933161B2
公开(公告)日：2011-04-26
申请号：US11509057
申请日：2006-08-24
申请人： Hideaki Miyamoto , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Shigeharu Matsushita
IPC分类号： G11C7/20
CPC分类号： G11C11/22
摘要： A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads data from and rewrites data in the memory cell in a power-down state.
摘要翻译：获得能够防止存储器单元从累积干扰导致的数据消失的存储器。该存储器包括非易失性存储器单元和用于重写存储单元中的数据的刷新部分。刷新部分在掉电状态下从存储器单元读取数据并重新写入数据。

3. 发明授权

US07379323B2 Memory with a refresh portion for rewriting data 有权
标题翻译：具有用于重写数据的刷新部分的内存
公开(公告)号：US07379323B2
公开(公告)日：2008-05-27
申请号：US11524273
申请日：2006-09-21
申请人： Hideaki Miyamoto , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Shigeharu Matsushita
IPC分类号： G11C11/22 , G11C11/406 , G06F12/00 , G06F13/00
CPC分类号： G11C11/22
摘要： This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies with respect to the plurality of memory cell blocks detected by the first frequency detecting portion with each other and a refresh portion exercising control for selecting a prescribed memory cell block from among the plurality of memory cell blocks on the basis of comparison data output from the comparator and preferentially rewriting data in the memory cells included in the selected memory cell block.
摘要翻译：该存储器包括分别检测相对于多个存储单元块的存取频率的第一频率检测部分，比较第一频率检测部分检测到的与多个存储单元块相关的存取频率的比较器和刷新基于从比较器输出的比较数据，从多个存储单元块中选择规定的存储单元块的部分运动控制，并优先地重写在所选择的存储单元块中包括的存储单元中的数据。

4. 发明申请

US20070237016A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20070237016A1
公开(公告)日：2007-10-11
申请号：US11630851
申请日：2005-06-16
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C7/00
CPC分类号： G11C11/22
摘要： A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell(12). During this access operation, it is performed to apply to the memory cell(12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell(12).
摘要翻译：可以抑制其中未选择的存储单元中的数据丢失的任何“干扰效应”的存储器。该存储器具有存储单元阵列（1），该存储单元阵列（1）包括位线，设置成与位线相交的字线以及每个连接在位线和字线之间的存储单元（12）。在该存储器中，对选择的存储器单元（12）进行包括读取，重写和写入操作中的至少一个的访问操作。在该访问操作期间，执行向存储器单元（12）施加第一电压脉冲，该第一电压脉冲在第一方向上提供电场以反转存储的数据，以及第二电压脉冲，其提供为电场与第一个方向相反的方向，以便不反转存储的数据。此外，对存储单元（12）进行用于恢复残留极化量的恢复操作。

5. 发明申请

US20070070764A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20070070764A1
公开(公告)日：2007-03-29
申请号：US11524273
申请日：2006-09-21
申请人： Hideaki Miyamoto , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Shigeharu Matsushita
IPC分类号： G11C7/00
CPC分类号： G11C11/22
摘要： This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies with respect to the plurality of memory cell blocks detected by the first frequency detecting portion with each other and a refresh portion exercising control for selecting a prescribed memory cell block from among the plurality of memory cell blocks on the basis of comparison data output from the comparator and preferentially rewriting data in the memory cells included in the selected memory cell block.
摘要翻译：该存储器包括分别检测相对于多个存储单元块的存取频率的第一频率检测部分，比较第一频率检测部分检测到的与多个存储单元块相关的存取频率的比较器和刷新基于从比较器输出的比较数据，从多个存储单元块中选择规定的存储单元块的部分运动控制，并优先地重写在所选择的存储单元块中包括的存储单元中的数据。

6. 发明授权

US07366004B2 Memory 有权
标题翻译：记忆
公开(公告)号：US07366004B2
公开(公告)日：2008-04-29
申请号：US11328223
申请日：2006-01-10
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.
摘要翻译：提供了能够抑制数据读取中的读取电压的降低而不管制造过程中的分散性的存储器。该存储器包括电荷存储装置，第一场效应晶体管和数据确定装置。存储器将第一场效应晶体管的控制端子和剩余的第一端子之间的电压设置为阈值电压，以使第一场效应晶体管处于ON和OFF之间的边界状态附近的截止状态 - 通过第一场效应晶体管的阈值电压。

7. 发明申请

US20070047363A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20070047363A1
公开(公告)日：2007-03-01
申请号：US11509057
申请日：2006-08-24
申请人： Hideaki Miyamoto , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Shigeharu Matsushita
IPC分类号： G11C5/14
CPC分类号： G11C11/22
摘要： A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads and rewrites data from and in the memory cell in a power-down state.
摘要翻译：获得能够防止存储器单元从累积干扰导致的数据消失的存储器。该存储器包括非易失性存储器单元和用于重写存储单元中的数据的刷新部分。刷新部分在掉电状态下读取和重写来自存储器单元的数据。

8. 发明申请

US20060164877A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20060164877A1
公开(公告)日：2006-07-27
申请号：US11328223
申请日：2006-01-10
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.
摘要翻译：提供了能够抑制数据读取中的读取电压的降低而不管制造过程中的分散性的存储器。该存储器包括电荷存储装置，第一场效应晶体管和数据确定装置。存储器将第一场效应晶体管的控制端子和剩余的第一端子之间的电压设置为阈值电压，以使第一场效应晶体管处于ON和OFF之间的边界状态附近的截止状态 - 通过第一场效应晶体管的阈值电压。

9. 发明授权

US07652908B2 Ferroelectric memory having a refresh control circuit capable of recovering residual polarization of unselected memory cells 有权
标题翻译：铁电存储器具有能够恢复未选择的存储单元的剩余极化的刷新控制电路
公开(公告)号：US07652908B2
公开(公告)日：2010-01-26
申请号：US11630851
申请日：2005-06-16
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array (1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells (12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell (12). During this access operation, it is performed to apply to the memory cell (12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell (12).
摘要翻译：可以抑制其中未选择的存储单元中的数据丢失的任何“干扰效应”的存储器。该存储器具有存储单元阵列（1），该存储单元阵列（1）包括位线，设置成与位线相交的字线以及各自连接在位线和字线之间的存储单元（12）。在该存储器中，对选择的存储器单元（12）进行包括读取，重写和写入操作中的至少一个的访问操作。在该访问操作期间，执行向存储器单元（12）施加第一电压脉冲，该第一电压脉冲在第一方向上提供电场以反转存储的数据，以及第二电压脉冲，其提供为电场与第一个方向相反的方向，以便不反转存储的数据。此外，对存储单元（12）进行用于恢复残留极化量的恢复操作。

10. 发明授权

US07362642B2 Memory 有权
标题翻译：记忆
公开(公告)号：US07362642B2
公开(公告)日：2008-04-22
申请号：US11494748
申请日：2006-07-28
申请人： Hideaki Miyamoto , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Shigeharu Matsushita
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C2211/4061
摘要： A memory allowing reduction of the period of an external access operation is provided. This memory comprises an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation and a refresh division control portion dividing the refresh operation into a read operation RFRD and rewrite operations RFRS1 and RFRS2. The memory performs the read operation RFRD and the rewrite operations RFRS1 and RFRS2 at least either before or after different internal access operations corresponding to different external access operations respectively.
摘要翻译：提供了允许减少外部访问操作的周期的存储器。该存储器包括访问控制部分，其基于外部访问操作执行内部访问操作，执行刷新操作的刷新控制部分和将刷新操作分为读取操作RFRD和重写操作RFRS 1的刷新分配控制部分，以及 RFRS 2。存储器分别在对应于不同外部访问操作的不同内部访问操作之前或之后至少执行读取操作RFRD和重写操作RFRS 1和RFRS 2。

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