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1. 发明授权

US08647821B2 Method and apparatus for combined electrochemical synthesis and detection of analytes 有权
标题翻译：用于组合电化学合成和分析物检测的方法和装置
公开(公告)号：US08647821B2
公开(公告)日：2014-02-11
申请号：US13726062
申请日：2012-12-22
申请人： Hernan A. Castro , Gordon D. Holt , Brandon C. Barnett , Handong Li , Narayanan Sundararajan , Wei Wang
发明人： Hernan A. Castro , Gordon D. Holt , Brandon C. Barnett , Handong Li , Narayanan Sundararajan , Wei Wang
IPC分类号： C12Q1/68 , C12M1/00 , C12M1/34 , C25B15/02 , G01R27/26 , H01G4/35 , G01N27/00 , C07H21/00
CPC分类号： C25B3/00 , G01N27/226 , H01M14/00
摘要： Described are devices and methods for detecting binding on an electrode surface. In addition, devices and methods for electrochemically synthesizing polymers and devices and methods for synthesizing and detecting binding to the polymer on a common integrated device surface are described.
摘要翻译：描述了用于检测电极表面上的结合的装置和方法。此外，描述了用于电化学合成聚合物的装置和方法以及用于合成和检测在共同的集成器件表面上与聚合物结合的方法。

2. 发明申请

US20140169089A1 PATH ISOLATION IN A MEMORY DEVICE 有权
标题翻译：存储器件中的路径隔离
公开(公告)号：US20140169089A1
公开(公告)日：2014-06-19
申请号：US13496378
申请日：2011-09-09
申请人： Hernan A. Castro
发明人： Hernan A. Castro
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C7/10 , G11C7/12 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/02 , G11C16/06
摘要： Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了在相变存储器（PCM）设备中的字线路径隔离的技术和配置。在一个实施例中，存储器件包括存储器件的存储器单元，耦合到存储器单元的位线，耦合到存储器单元的字线，耦合到位线的位线电极，字耦合到字线的选择模块的限流电路，耦合到具有较低电位的字线电极和位线电极之一的选择模块的限流电路，所述限流电路有助于选择操作存储单元，所述感测电路耦合到所述字线电极和具有较低电位的所述位线电极之一，所述感测电路执行所述存储单元的读取操作，以及耦合到所述存储单元的写入电路的字线电极和具有较低电位的位线电极，写电路执行存储单元的写操作。可以描述和/或要求保护其他实施例。

3. 发明授权

US07583559B2 Two transistor wordline decoder output driver 失效
标题翻译：两个晶体管字线解码器输出驱动
公开(公告)号：US07583559B2
公开(公告)日：2009-09-01
申请号：US11756419
申请日：2007-05-31
申请人： Hari Giduturi , Mark Bauer , Hernan A. Castro
发明人： Hari Giduturi , Mark Bauer , Hernan A. Castro
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal.
摘要翻译：通常描述用于存储器件的字线解码器方案。在一个示例中，存储器件包括分布式逻辑“或”门，用于解码寻址信号以在存储器块内产生字线选择信号，其中分布逻辑或非门包括字线解码器输出驱动器，字线解码器输出驱动器包括与字线信号。

4. 发明授权

US5247206A Neural network accommodating parallel synaptic weight adjustments in a single cycle 失效
标题翻译：神经网络在单个周期内容纳平行突触体重调节
公开(公告)号：US5247206A
公开(公告)日：1993-09-21
申请号：US885528
申请日：1992-05-19
申请人： Hernan A. Castro
发明人： Hernan A. Castro
IPC分类号： G06N3/063
CPC分类号： G06N3/063
摘要： A neural network providing correlation learning in a synapse cell coupled to a circuit for parallel implementation of weight adjustment provides the learning portion of the synaptic operation and includes a floating gate device having a corresponding floating gate member that stores the connection weight of the cell. Parallel weight adjustments are performed in a single operational cycle utilizing floating gate technology and control signals that facilitate programming/erasing operations.
摘要翻译：提供耦合到用于并行实施权重调整的电路的突触细胞中的相关学习的神经网络提供突触操作的学习部分，并且包括具有存储单元的连接权重的相应浮动门构件的浮动栅极器件。使用浮动栅极技术和便于编程/擦除操作的控制信号，在单个操作周期内执行平行重量调整。

5. 发明授权

US5155377A Charge domain differential conductance synapse cell for neural networks 失效
标题翻译：神经网络的电荷域微分电导突触细胞
公开(公告)号：US5155377A
公开(公告)日：1992-10-13
申请号：US821634
申请日：1992-01-16
申请人： Hernan A. Castro
发明人： Hernan A. Castro
IPC分类号： G06N3/063
CPC分类号： G06N3/0635
摘要： A semiconductor charge transfer synapse cell has a capacitor coupled between an input line and an intermediate node. A voltage pulse applied to the input line causes charge transfer from one summing line to another through a pair of series connected field-effect devices. Each of the devices has an associated gate potential which controls its resistance. In response to the low-to-high voltage transition of the input pulse current flows through the devices from the intermediate node to the summing lines. A high-to-low transition causes current to flow in the opposite direction. Because the relative conductances of the devices are different depending on the direction of current flow, a net charge is transferred from one summing line to the other. The amount of charge transferred is a function of the amplitude of the pulsed input, the gate potentials, and the capacitance value.
摘要翻译：半导体电荷转移突触电池具有耦合在输入线和中间节点之间的电容器。施加到输入线的电压脉冲通过一对串联的场效应器件将电荷从一个求和线传输到另一个。每个器件具有控制其电阻的相关联的栅极电位。响应于输入脉冲的低电压到高电压转换，电流从中间节点流向相加线路。从高到低的转换导致电流沿相反的方向流动。由于设备的相对电导根据电流的方向而不同，净电荷从一个求和线传输到另一个。转移的电荷量是脉冲输入的幅度，栅极电位和电容值的函数。

6. 发明授权

US5136176A Charge domain synapse cell 失效
标题翻译：电荷域突触细胞
公开(公告)号：US5136176A
公开(公告)日：1992-08-04
申请号：US747640
申请日：1991-08-20
申请人： Hernan A. Castro
发明人： Hernan A. Castro
IPC分类号： G06F15/18 , G06G7/60 , G06N3/063 , H03K17/30
CPC分类号： G06N3/0635 , G06N3/063
摘要： A semiconductor charge domain synapse cell has a capacitor coupled between an input line and an intermediate node. A high-to-low voltage transition applied to the input line causes charge transfer from one summing line to the intermediate node through a first device having a programmable threshold. A second device then transfers the charge from the intermediate node to another summing line in response to the next low-to-high transition of the input. The amount of charge transferred is proportional the amplitude of the pulsed input, the programmed voltage threshold, and the capacitance value.
摘要翻译：半导体电荷域突触电池具有耦合在输入线和中间节点之间的电容器。施加到输入线的高电平到低电压转换通过具有可编程阈值的第一器件使得从一个求和线到中间节点的电荷转移。然后，响应于输入的下一个低到高的转换，第二设备将电荷从中间节点传送到另一求和线。传输的电荷量与脉冲输入的幅度，编程的电压阈值和电容值成比例。

7. 发明授权

US5075869A Neural network exhibiting improved tolerance to temperature and power supply variations 失效
标题翻译：显示改善的耐温度和电源变化的神经网络
公开(公告)号：US5075869A
公开(公告)日：1991-12-24
申请号：US557555
申请日：1990-06-24
申请人： Mark A. Holler , Hernan A. Castro , Simon M. Tam
发明人： Mark A. Holler , Hernan A. Castro , Simon M. Tam
IPC分类号： G06N3/063
CPC分类号： G06N3/0635
摘要： An analog neural network is described which provides a means for reducing the sensitivity of the network to temperature and power supply variations. A first circuit is utilized for generating a signal which exhibits a dependence on temperature corresponding to the variation normally experienced by the network in response to a change in temperature. A second circuit is employed to generate another signal which exhibits a similar dependence, except on power supply variations. By coupling these signals as inputs to the neural network the sensitivity of the network to temperature and power supply fluctuations is essentially nulified.
摘要翻译：描述了一种模拟神经网络，其提供了降低网络对温度和电源变化的灵敏度的手段。第一电路用于产生对应于温度变化通常由网络经历的变化的温度的依赖性的信号。除了电源变化之外，使用第二电路产生表现出相似依赖性的另一信号。通过将这些信号作为输入耦合到神经网络，网络对温度和电源波动的敏感度基本上是nulified。

8. 发明授权

US5039941A Voltage threshold measuring circuit 失效
标题翻译：电压门限测量电路
公开(公告)号：US5039941A
公开(公告)日：1991-08-13
申请号：US559361
申请日：1990-07-27
申请人： Hernan A. Castro
发明人： Hernan A. Castro
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： A circuit for determining the voltage threshold of a field-effect device is described. The invention includes an amplifier means which produces an output voltage directly proportional to the current flowing within the device-under-test. A circuit means is utilized for receiving the output voltage from the amplifier means and for generating a feedback voltage at the gate of the field-effect device. This feedback voltage is dynamically limited by an RC time constant such that the feedback voltage rapidly settles to the voltage threshold of the field-effect device.
摘要翻译：描述用于确定场效应装置的电压阈值的电路。本发明包括放大器装置，该放大器装置产生与在待测器件内流动的电流成正比的输出电压。电路装置用于从放大器装置接收输出电压并在场效应装置的栅极处产生反馈电压。该反馈电压由RC时间常数动态地限制，使得反馈电压快速地稳定在场效应器件的电压阈值。

9. 发明授权

US4956564A Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network 失效
标题翻译：自适应突触细胞在联想网络中提供兴奋性和抑制性连接
公开(公告)号：US4956564A
公开(公告)日：1990-09-11
申请号：US379933
申请日：1989-07-13
申请人： Mark A. Holler , Simon M. Tam , Hernan A. Castro
发明人： Mark A. Holler , Simon M. Tam , Hernan A. Castro
IPC分类号： G11C11/54 , G06N3/063 , G11C15/04
CPC分类号： G06N3/0635 , G06N3/063 , G11C15/046
摘要： The present invention covers a synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using one or more floating-gate transistors which provide both excitatory as well as inhibitory connections. As configured, each transistor's control gate is coupled to an input line and its drain is coupled to an output summing line. The floating-gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to the control gate of the floating-gate transistor, a current is generated which acts to discharge the capacitance associated with the output summing line. The current, and therefore the resulting discharge, is directly proportional to the charge stored on the floating-gate member and the duration of the input pulse.
摘要翻译：本发明涵盖用于在输入电压线和具有相关电容的输出求和线之间提供加权连接的突触电池。关联网络中的输入和输出线之间的连接是使用一个或多个提供兴奋性和抑制性连接两者的浮栅晶体管进行的。如所配置的，每个晶体管的控制栅极耦合到输入线，并且其漏极耦合到输出求和线。晶体管的浮置栅极用于存储对应于神经连接的强度或重量的电荷。当具有一定持续时间的二进制电压脉冲被施加到浮栅晶体管的控制栅极时，产生用于放电与输出求和线相关联的电容的电流。电流，因此产生的放电与存储在浮栅器件上的电荷和输入脉冲的持续时间成正比。

10. 发明授权

US08917534B2 Path isolation in a memory device 有权
标题翻译：存储设备中的路径隔离
公开(公告)号：US08917534B2
公开(公告)日：2014-12-23
申请号：US13496378
申请日：2011-09-09
申请人： Hernan A. Castro
发明人： Hernan A. Castro
IPC分类号： G11C11/00 , G11C13/00 , G11C16/06 , G11C7/10 , G11C7/12 , G11C13/02
CPC分类号： G11C13/0097 , G11C7/10 , G11C7/12 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/02 , G11C16/06
摘要： Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了在相变存储器（PCM）设备中的字线路径隔离的技术和配置。在一个实施例中，存储器件包括存储器件的存储器单元，耦合到存储器单元的位线，耦合到存储器单元的字线，耦合到位线的位线电极，字耦合到字线的选择模块的限流电路，耦合到具有较低电位的字线电极和位线电极之一的选择模块的限流电路，所述限流电路有助于选择操作存储单元，所述感测电路耦合到所述字线电极和具有较低电位的所述位线电极之一，所述感测电路执行所述存储单元的读取操作，以及耦合到所述存储单元的写入电路的字线电极和具有较低电位的位线电极，写电路执行存储单元的写操作。可以描述和/或要求保护其他实施例。

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