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    • 1. 发明授权
    • Clock voltage supply
    • 时钟电压供应
    • US4788670A
    • 1988-11-29
    • US86428
    • 1987-08-18
    • Hermann HofmannDavid JohnsonWerner SchirlHans-Peter Troendle
    • Hermann HofmannDavid JohnsonWerner SchirlHans-Peter Troendle
    • G04G3/00G06F1/04G06F1/12G04F8/00H03L7/00
    • G06F1/12G04G3/00G06F1/04
    • A clock voltage supply for electronic control circuits such as a computer system for generating four clock signals which are synchronous as to frequency and phase. When n=4, the clock signals are generated with the help of four PLL clocks. So that the four clock signals can continue to appear even if one of the four clocks is malfunctioning, the clock signals of the four clocks are supplied to four (3:4) voters from whose outputs the clock signals are then supplied. Since each voter circuit brings about a certain delay time, which significantly limits the frequency of the clock signals, a delay element is connected downstream to each of the voter outputs respectively. The delay time of the respective delay element, plus the delay time of the respective voter connected therewith, is an integral multiple of the period of the intended clock frequency. For PLL control, the output of each delay element gives the nominal phase position and the output of each clock gives the actual phase position.
    • 用于诸如计算机系统的电子控制电路的时钟电压源,用于产生与频率和相位同步的四个时钟信号。 当n = 4时,通过四个PLL时钟产生时钟信号。 因此,即使四个时钟之一发生故障,四个时钟信号也可以继续出现,四个时钟的时钟信号被提供给四(3:4)个选择器,其输出端随后提供时钟信号。 由于每个选举电路产生一定的延迟时间,这明显地限制了时钟信号的频率,延迟元件分别连接到每个选举输出的下游。 各个延迟元件的延迟时间加上与其连接的各个选民的延迟时间是期望的时钟频率的周期的整数倍。 对于PLL控制,每个延迟元件的输出给出标称相位位置,每个时钟的输出给出实际的相位位置。