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1. 发明授权

US07755713B2 Peripheral circuit 有权
标题翻译：外设电路
公开(公告)号：US07755713B2
公开(公告)日：2010-07-13
申请号：US12234700
申请日：2008-09-21
申请人： Heng-Chang Lin , Yu-Fang Wang , Ming-Kang Huang , Chih-Kun Lin
发明人： Heng-Chang Lin , Yu-Fang Wang , Ming-Kang Huang , Chih-Kun Lin
IPC分类号： G02F1/1333 , G02F1/1345 , G01R31/00
CPC分类号： G02F1/13452 , G02F2001/136254
摘要： A peripheral circuit disposed on a substrate having an active device array is provided. The peripheral circuit includes first test pads, second test pads, first lines, and second lines. The first and the second lines are electrically connected to the active device array. Each first test pad includes a first conductive layer and a second conductive layer electrically connected to the first conductive layer. The first conductive layer electrically connects at least two of the adjacent first lines. The second test pads are interposed between the first test pads and the active device array. Each second test pad includes third conductive layers and a fourth conductive layer electrically connected to the third conductive layers. The first lines pass through the third conductive layers and are insulated from the fourth conductive layer. Each third conductive layer is electrically connected to one of the adjacent second lines respectively.
摘要翻译：设置在具有有源器件阵列的衬底上的外围电路。外围电路包括第一测试焊盘，第二测试焊盘，第一线和第二线。第一和第二线电连接到有源器件阵列。每个第一测试焊盘包括电连接到第一导电层的第一导电层和第二导电层。第一导电层电连接相邻第一线中的至少两个。第二测试焊盘插入在第一测试焊盘和有源器件阵列之间。每个第二测试焊盘包括第三导电层和与第三导电层电连接的第四导电层。第一线穿过第三导电层并与第四导电层绝缘。每个第三导电层分别电连接到相邻的第二线之一。

2. 发明申请

US20090207369A1 PERIPHERAL CIRCUIT 有权
标题翻译：外围电路
公开(公告)号：US20090207369A1
公开(公告)日：2009-08-20
申请号：US12234700
申请日：2008-09-21
申请人： Heng-Chang Lin , Yu-Fang Wang , Ming-Kang Huang , Chih-Kun Lin
发明人： Heng-Chang Lin , Yu-Fang Wang , Ming-Kang Huang , Chih-Kun Lin
IPC分类号： G02F1/1345
CPC分类号： G02F1/13452 , G02F2001/136254
摘要： A peripheral circuit disposed on a substrate having an active device array is provided. The peripheral circuit includes first test pads, second test pads, first lines, and second lines. The first and the second lines are electrically connected to the active device array. Each first test pad includes a first conductive layer and a second conductive layer electrically connected to the first conductive layer. The first conductive layer electrically connects at least two of the adjacent first lines. The second test pads are interposed between the first test pads and the active device array. Each second test pad includes third conductive layers and a fourth conductive layer electrically connected to the third conductive layers. The first lines pass through the third conductive layers and are insulated from the fourth conductive layer. Each third conductive layer is electrically connected to one of the adjacent second lines respectively.
摘要翻译：设置在具有有源器件阵列的衬底上的外围电路。外围电路包括第一测试焊盘，第二测试焊盘，第一线和第二线。第一和第二线电连接到有源器件阵列。每个第一测试焊盘包括电连接到第一导电层的第一导电层和第二导电层。第一导电层电连接相邻第一线中的至少两个。第二测试焊盘插入在第一测试焊盘和有源器件阵列之间。每个第二测试焊盘包括第三导电层和与第三导电层电连接的第四导电层。第一线穿过第三导电层并与第四导电层绝缘。每个第三导电层分别电连接到相邻的第二线之一。

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