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1. 发明授权

US09563466B2 Method and apparatus for supporting programmable software context state execution during hardware context restore flow 有权
标题翻译：用于在硬件上下文恢复流程期间支持可编程软件上下文状态执行的方法和装置
公开(公告)号：US09563466B2
公开(公告)日：2017-02-07
申请号：US14072622
申请日：2013-11-05
申请人： Hema Chand Nalluri , Jeffery S. Boles , Murali Ramadoss , Aditya Navale , Lalit K. Saptarshi
发明人： Hema Chand Nalluri , Jeffery S. Boles , Murali Ramadoss , Aditya Navale , Lalit K. Saptarshi
IPC分类号： G06F9/46 , G06T1/20
CPC分类号： G06F9/461 , G06T1/20
摘要： A method and apparatus for supporting programmable software context state execution during hardware context restore flow is described. In one example, a context ID is assigned to graphics applications including a unique context memory buffer, a unique indirect context pointer and a corresponding size to each context ID, an indirect context offset, and an indirect context buffer address range. When execution of the first context workload is indirected, the state of the first context workload is saved to the assigned context memory buffer. The indirect context pointer, the indirect context offset and a size of the indirect context buffer address range are saved to registers that are independent of the saved context state. The context is restored by accessing the saved indirect context pointer, the indirect context offset and the buffer size.
摘要翻译：描述了用于在硬件上下文恢复流程期间支持可编程软件上下文状态执行的方法和装置。在一个示例中，上下文ID被分配给包括唯一上下文存储器缓冲器，唯一间接上下文指针和对每个上下文ID，间接上下文偏移以及间接上下文缓冲器地址范围的对应大小的图形应用。当第一上下文工作负载的执行被间接时，第一上下文工作负载的状态被保存到所分配的上下文存储器缓冲器中。间接上下文指针，间接上下文偏移量和间接上下文缓冲区地址范围的大小保存到独立于保存的上下文状态的寄存器中。通过访问保存的间接上下文指针，间接上下文偏移量和缓冲区大小来恢复上下文。

2. 发明申请

US20150002522A1 MID COMMAND BUFFER PREEMPTION FOR GRAPHICS WORKLOADS 有权
标题翻译：图形工作负载的MID命令缓冲区预处理
公开(公告)号：US20150002522A1
公开(公告)日：2015-01-01
申请号：US13931915
申请日：2013-06-29
申请人： Hema Chand Nalluri , Aditya Navale , Murali Ramadoss , Jeffery S. Boles
发明人： Hema Chand Nalluri , Aditya Navale , Murali Ramadoss , Jeffery S. Boles
IPC分类号： G06T1/20
CPC分类号： G06T1/60 , G06F9/48 , G06F9/485 , G06T1/20
摘要： Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.
摘要翻译：描述图形处理环境中图形工作负载的中间命令缓冲区抢占。在一个示例中，在图形处理器处执行第一上下文的指令，第一上下文在可寻址缓冲器中具有指令序列，并且指令中的至少一个是抢占指令。在执行抢占指令之后，在指令序列完成之前停止第一上下文的执行。存储用于第一上下文将被恢复的指令的地址。执行第二上下文，并且在完成第二上下文的执行时，在存储的地址处恢复执行第一上下文。

3. 发明授权

US09659342B2 Mid command buffer preemption for graphics workloads 有权
公开(公告)号：US09659342B2
公开(公告)日：2017-05-23
申请号：US13931915
申请日：2013-06-29
申请人： Hema Chand Nalluri , Aditya Navale , Murali Ramadoss , Jeffery S. Boles
发明人： Hema Chand Nalluri , Aditya Navale , Murali Ramadoss , Jeffery S. Boles
IPC分类号： G06F9/48 , G06T1/60 , G06T1/20
CPC分类号： G06T1/60 , G06F9/48 , G06F9/485 , G06T1/20
摘要： Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.

4. 发明申请

US20150123980A1 METHOD AND APPARATUS FOR SUPPORTING PROGRAMMABLE SOFTWARE CONTEXT STATE EXECUTION DURING HARDWARE CONTEXT RESTORE FLOW 有权
标题翻译：在硬件上下文恢复流程期间支持可编程软件上下文执行的方法和装置
公开(公告)号：US20150123980A1
公开(公告)日：2015-05-07
申请号：US14072622
申请日：2013-11-05
申请人： Hema Chand Nalluri , Jeffery S. Boles , Murali Ramadoss , Aditya Navale , Lalit K. Saptarshi
发明人： Hema Chand Nalluri , Jeffery S. Boles , Murali Ramadoss , Aditya Navale , Lalit K. Saptarshi
IPC分类号： G06T15/00 , G06F9/46 , G06T1/20
CPC分类号： G06F9/461 , G06T1/20
摘要： A method and apparatus for supporting programmable software context state execution during hardware context restore flow is described. In one example, a context ID is assigned to graphics applications including a unique context memory buffer, a unique indirect context pointer and a corresponding size to each context ID, an indirect context offset, and an indirect context buffer address range. When execution of the first context workload is indirected, the state of the first context workload is saved to the assigned context memory buffer. The indirect context pointer, the indirect context offset and a size of the indirect context buffer address range are saved to registers that are independent of the saved context state. The context is restored by accessing the saved indirect context pointer, the indirect context offset and the buffer size.
摘要翻译：描述了用于在硬件上下文恢复流程期间支持可编程软件上下文状态执行的方法和装置。在一个示例中，上下文ID被分配给包括唯一上下文存储器缓冲器，唯一间接上下文指针和对每个上下文ID，间接上下文偏移以及间接上下文缓冲器地址范围的对应大小的图形应用。当第一上下文工作负载的执行被间接时，第一上下文工作负载的状态被保存到所分配的上下文存储器缓冲器中。间接上下文指针，间接上下文偏移量和间接上下文缓冲区地址范围的大小保存到独立于保存的上下文状态的寄存器中。通过访问保存的间接上下文指针，间接上下文偏移量和缓冲区大小来恢复上下文。

5. 发明申请

US20150277981A1 PRIORITY BASED CONTEXT PREEMPTION 有权
标题翻译：基于优先级的语境预测
公开(公告)号：US20150277981A1
公开(公告)日：2015-10-01
申请号：US14227692
申请日：2014-03-27
申请人： Hema C. Nalluri , Aditya Navale , Peter L. Doyle , Murali Ramadoss , Balaji Vembu , Jeffery S. Boles
发明人： Hema C. Nalluri , Aditya Navale , Peter L. Doyle , Murali Ramadoss , Balaji Vembu , Jeffery S. Boles
IPC分类号： G06F9/50 , G06T1/20
CPC分类号： G06F9/5038 , G06T1/20
摘要： Methods and apparatuses may prioritize the processing of high priority and low priority contexts submitted to a processing unit through separate high priority and low priority context submission ports. According to one embodiment, submission of a context to the low priority port causes contexts in progress to be preempted, whereas submission of a context to the high priority port causes contexts in progress to be paused.
摘要翻译：方法和设备可以优先处理通过单独的高优先级和低优先级上下文提交端口提交给处理单元的高优先级和低优先权上下文。根据一个实施例，向低优先级端口提交上下文导致正在进行的上下文被抢占，而向高优先级端口提交上下文导致正在进行的上下文被暂停。

6. 发明申请

US20170091989A1 Position Only Shader Context Submission Through a Render Command Streamer 审中-公开
公开(公告)号：US20170091989A1
公开(公告)日：2017-03-30
申请号：US14865933
申请日：2015-09-25
申请人： Murali Ramadoss , Balaji Vembu , Hema C. Nalluri , Michael Apodaca , Jeffery S. Boles
发明人： Murali Ramadoss , Balaji Vembu , Hema C. Nalluri , Michael Apodaca , Jeffery S. Boles
IPC分类号： G06T15/80 , G06T1/20
CPC分类号： G06T15/80 , G06F9/48 , G06F9/4881 , G06T1/20
摘要： By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.

7. 发明申请

US20140104287A1 HARDWARE ASSIST FOR PRIVILEGE ACCESS VIOLATION CHECKS 有权
标题翻译：用于特权入侵检查的硬件助理
公开(公告)号：US20140104287A1
公开(公告)日：2014-04-17
申请号：US13649798
申请日：2012-10-11
申请人： Hema C. Nalluri , Aditya Navale , Murali Ramadoss
发明人： Hema C. Nalluri , Aditya Navale , Murali Ramadoss
IPC分类号： G06T15/00
CPC分类号： G06F21/74 , G06F21/84 , G06T15/005
摘要： Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU
摘要翻译：公开了用于以安全方式处理图形系统的渲染引擎工作负载的技术，其中将工作负载的至少一些安全处理从基于软件的安全解析卸载到基于硬件的安全解析。在一些实施例中，来自给定应用的命令由用户模式驱动程序（UMD）接收，用户模式驱动程序（UMD）被配置为生成描绘为特权和/或非特权命令部分的命令缓冲器。所描绘的命令缓冲区然后可以被UMD传递给内核模式驱动程序（KMD），该驱动程序被配置为仅解析和验证特权缓冲区段，而是发出所有其他批处理缓冲区，其特权指示符设置为非特权。图形处理单元（GPU）可以从KMD接收特权指定的批量缓冲区，并且配置为不允许从非特权批处理缓冲区执行任何特权命令，而来自特权批处理缓冲区的任何特权命令都不受GPU限制

8. 发明授权

US09304813B2 CPU independent graphics scheduler for performing scheduling operations for graphics hardware 有权
标题翻译： CPU独立的图形调度程序，用于执行图形硬件的调度操作
公开(公告)号：US09304813B2
公开(公告)日：2016-04-05
申请号：US13552122
申请日：2012-07-18
申请人： Balaji Vembu , Aditya Navale , Murali Ramadoss , David I. Standring , Kritika Bala
发明人： Balaji Vembu , Aditya Navale , Murali Ramadoss , David I. Standring , Kritika Bala
IPC分类号： G06F9/46 , G06F15/16 , G06F7/38 , G06F9/48
CPC分类号： G06F9/4881 , Y02D10/24
摘要： A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.
摘要翻译：本文描述了用于执行图形硬件的调度操作的计算设备。计算设备包括被配置为执行应用的中央处理单元（CPU）。计算设备还包括被配置为独立于CPU操作的图形调度器。图形调度器被配置为接收与在CPU上执行的应用程序的工作负载有关的工作队列，并且基于工作队列对多个图形引擎中的任何一个执行调度操作。

9. 发明授权

US09678795B2 Direct ring 3 submission of processing jobs to adjunct processors 有权
公开(公告)号：US09678795B2
公开(公告)日：2017-06-13
申请号：US13993089
申请日：2011-12-30
申请人： Altug Koker , Aditya Navale , Balaji Vembu , Murali Ramadoss
发明人： Altug Koker , Aditya Navale , Balaji Vembu , Murali Ramadoss
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48 , G06F15/167 , G06F9/54 , G06F12/14
CPC分类号： G06F9/50 , G06F9/4812 , G06F9/545 , G06F12/1491 , G06F15/167
摘要： Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

10. 发明申请

US20140026137A1 PERFORMING SCHEDULING OPERATIONS FOR GRAPHICS HARDWARE 有权
标题翻译：执行图形硬件的调度操作
公开(公告)号：US20140026137A1
公开(公告)日：2014-01-23
申请号：US13552122
申请日：2012-07-18
申请人： Balaji Vembu , Aditya Navale , Murali Ramadoss , David I. Standring , Kritika Bala
发明人： Balaji Vembu , Aditya Navale , Murali Ramadoss , David I. Standring , Kritika Bala
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , Y02D10/24
摘要： A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.
摘要翻译：本文描述了用于执行图形硬件的调度操作的计算设备。计算设备包括被配置为执行应用的中央处理单元（CPU）。计算设备还包括被配置为独立于CPU操作的图形调度器。图形调度器被配置为接收与在CPU上执行的应用程序的工作负载有关的工作队列，并且基于工作队列对多个图形引擎中的任何一个执行调度操作。

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