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1. 发明申请

US20060012499A1 Converter, circuit and method for compensation of non-idealities in continuous time sigma delta converters 有权
标题翻译：用于补偿连续时间Σ-Δ转换器中非理想度的转换器，电路和方法
公开(公告)号：US20060012499A1
公开(公告)日：2006-01-19
申请号：US10534119
申请日：2003-11-03
申请人： Hassan Ihs , Babak Bastani , Jalal Ouaddah
发明人： Hassan Ihs , Babak Bastani , Jalal Ouaddah
IPC分类号： H03M3/00
CPC分类号： H03M3/352 , H03M3/422
摘要： A continuous time sigma delta converter has a filter and converter components having known non-ideal characteristics. A compensation circuit has error modelling components arranged to model the non-ideal characteristics of the converter. A summation block combines a compensation signal from the compensation circuit with a non-ideal output signal from the converter in order to provide a compensated output signal. This has substantially no effect on other modulator performance characteristics and contributes to the implementation of giga sample-per-second Continuous Time sigma deltas having the dynamic range capabilities of traditional DT sigma deltas.
摘要翻译：连续时间Σ-Δ转换器具有具有已知非理想特性的滤波器和转换器组件。补偿电路具有错误建模部件，用于对转换器的非理想特性进行建模。求和块将来自补偿电路的补偿信号与来自转换器的非理想输出信号相结合，以提供经补偿的输出信号。这对其他调制器性能特征基本上没有影响，并且有助于实现具有传统DT西格玛三角形的动态范围能力的千兆每秒连续时间西格玛三角形。

2. 发明授权

US07245246B2 Converter, circuit and method for compensation of non-idealities in continuous time sigma delta converters 有权
标题翻译：用于补偿连续时间Σ-Δ转换器中非理想度的转换器，电路和方法
公开(公告)号：US07245246B2
公开(公告)日：2007-07-17
申请号：US10534119
申请日：2003-11-03
申请人： Hassan Ihs , Babak Bastani , Jalal Ouaddah
发明人： Hassan Ihs , Babak Bastani , Jalal Ouaddah
IPC分类号： H03M3/00
CPC分类号： H03M3/352 , H03M3/422
摘要： A continuous time sigma delta converter has a filter and converter components having known non-ideal characteristics. A compensation circuit has error modelling components arranged to model the non-ideal characteristics of the converter. A summation block combines a compensation signal from the compensation circuit with a non-ideal output signal from the converter in order to provide a compensated output signal. This has substantially no effect on other modulator performance characteristics and contributes to the implementation of giga sample-per-second Continuous Time sigma deltas having the dynamic range capabilities of traditional DT sigma deltas.
摘要翻译：连续时间Σ-Δ转换器具有具有已知非理想特性的滤波器和转换器组件。补偿电路具有错误建模部件，用于对转换器的非理想特性进行建模。求和块将来自补偿电路的补偿信号与来自转换器的非理想输出信号相结合，以提供经补偿的输出信号。这对其他调制器性能特征基本上没有影响，并且有助于实现具有传统DT西格玛三角形的动态范围能力的千兆每秒连续时间西格玛三角形。

3. 发明申请

US20210234461A1 THREE STAGE POWER DELIVERY SYSTEM 有权
公开(公告)号：US20210234461A1
公开(公告)日：2021-07-29
申请号：US17161426
申请日：2021-01-28
申请人： Hassan Ihs
发明人： Hassan Ihs
IPC分类号： H02M3/07 , H02J7/00
摘要： A power delivery system may include a first voltage regulator configured to output an upper intermediate voltage about an expected discharge voltage plateau of a battery for use by the power delivery system, a switched capacitive charge pump configured to down convert the upper intermediate voltage of the first voltage regulator to a lower intermediate voltage, and a second voltage regulator configured to use the lower intermediate voltage to provide power to a load.

4. 发明申请

US20180316265A1 BOOST DC-DC CONVERTER HAVING DIGITAL CONTROL AND REFERENCE PWM GENERATORS 审中-公开
公开(公告)号：US20180316265A1
公开(公告)日：2018-11-01
申请号：US16028202
申请日：2018-07-05
申请人： Hassan Ihs
发明人： Hassan Ihs
IPC分类号： H02M3/157 , H02M3/158 , H02M3/156
CPC分类号： H02M3/157 , H02M3/156 , H02M3/158 , H02M3/1588 , H02M2001/0025 , H02M2003/1566 , Y02B70/1466
摘要： A boost DC-DC converter operating in pulse frequency modulation (PFM) and pulse width modulation (PWM) modes includes a plurality of PWM signal generators. The PWM signal generators generate PWM signals with different duty cycles. PWM signals with larger duty cycles may be selected for use in undervoltage situations.

5. 发明申请

US20170170728A1 BOOST DC-DC CONVERTER HAVING DIGITAL CONTROL AND REFERENCE PWM GENERATORS 审中-公开
公开(公告)号：US20170170728A1
公开(公告)日：2017-06-15
申请号：US15376143
申请日：2016-12-12
申请人： Hassan Ihs
发明人： Hassan Ihs
IPC分类号： H02M3/157
CPC分类号： H02M3/157 , H02M3/156 , H02M3/158 , H02M3/1588 , Y02B70/1466
摘要： A boost DC-DC converter operating in pulse frequency modulation (PFM) and pulse width modulation (PWM) modes includes a plurality of PWM signal generators. The PWM signal generators generate PWM signals with different duty cycles. PWM signals with larger duty cycles may be selected for use in undervoltage situations.

6. 发明申请

US20110006938A1 SIGMA-DELTA MODULATOR APPARATUS AND METHOD OF GENERATING A MODULATED OUTPUT SIGNAL 有权
标题翻译： SIGMA-DELTA调制器装置和产生调制输出信号的方法
公开(公告)号：US20110006938A1
公开(公告)日：2011-01-13
申请号：US12866248
申请日：2008-02-13
申请人： Hassan Ihs , Frederic Schrive
发明人： Hassan Ihs , Frederic Schrive
IPC分类号： H03M3/02
CPC分类号： H03F3/2175 , H03M3/344 , H03M3/376 , H03M3/43 , H03M3/454
摘要： A discrete time sigma-delta modulator apparatus for class-D operation comprises a feed-forward path having an input at one end thereof and an output at another end thereof. A first summation unit is coupled in the feed-forward path to a first integrator. A quantizer is coupled in the feed-forward path after the first integrator and a feedback path arrangement is coupled to an input of the first summation unit. A low pass filter is arranged in the feedback path arrangement so as only to drive the first integrator.
摘要翻译：用于D类操作的离散时间Σ-Δ调制器装置包括在其一端具有输入的前馈路径和在其另一端的输出。第一求和单元在前馈路径中耦合到第一积分器。量化器在第一积分器之后的前馈路径中耦合，并且反馈路径布置耦合到第一求和单元的输入。在反馈路径布置中布置低通滤波器，以便仅驱动第一积分器。

7. 发明授权

US10840869B2 Capacitive MEMS microphone with active compression 有权
公开(公告)号：US10840869B2
公开(公告)日：2020-11-17
申请号：US16536244
申请日：2019-08-08
申请人： Hassan Ihs
发明人： Hassan Ihs
IPC分类号： H04R3/00 , H03F3/183 , H03G3/20 , H03M3/00 , H03G3/30 , H03M1/12 , H04R1/04
CPC分类号： H03G3/3005 , H03F3/183 , H03M1/12 , H03M3/30 , H04R1/04
摘要： A digital microphone compresses a large voltage swing signal from a MEMS capacitor to a signal suitable for processing by integrated circuitry. The compression may be performed in an analog domain by selectively coupling adjustment capacitors in parallel to the MEMS capacitor. The digital microphone may decompress the signal in the digital domain using a decompression technique substantially an inverse of the compression performed in the analog domain.

8. 发明授权

US10320282B2 Voltage regulator voltage overshoot look-back 有权
公开(公告)号：US10320282B2
公开(公告)日：2019-06-11
申请号：US16007968
申请日：2018-06-13
申请人： Bertrand Diotte , Jason Rau , Hassan Ihs
发明人： Bertrand Diotte , Jason Rau , Hassan Ihs
IPC分类号： H02M3/157 , H02M1/32 , H02M1/08 , H02M3/158
摘要： A deglitch circuit, or look-back, may be used to reduce or avoid reacting to a transient overvoltage situation by a voltage regulator. The voltage regulator may delay reacting to an overvoltage situation unless the overvoltage situation persists for more than a first programmable number of cycles.

9. 发明授权

US07409621B2 On-chip jitter testing 失效
标题翻译：片上抖动测试
公开(公告)号：US07409621B2
公开(公告)日：2008-08-05
申请号：US10331122
申请日：2002-12-26
申请人： Hassan Ihs , Salem Abdennadher
发明人： Hassan Ihs , Salem Abdennadher
IPC分类号： G01R31/317 , G01R31/40
CPC分类号： G01R31/3171 , G01R31/31709 , G01R31/31725 , G01R31/3187 , G01R31/31937
摘要： On-chip jitter testing includes providing a clock signal to a circuit under test and delaying outputs from the circuit under test by predetermined delay values. For each delay value, a corresponding output from the circuit under test is compared with a reference signal derived from the clock signal to produce a bit error rate count for each delay value. A jitter value in the output of the circuit under test is determined based on the bit error rate counts.
摘要翻译：片上抖动测试包括向被测电路提供时钟信号，并通过预定的延迟值延迟被测电路的输出。对于每个延迟值，将来自被测电路的相应输出与从时钟信号导出的参考信号进行比较，以产生每个延迟值的误码率计数。基于误码率计数确定被测电路的输出抖动值。

10. 发明申请

US20070164884A1 Clock pulse generator apparatus with reduced jitter clock phase 审中-公开
标题翻译：时钟脉冲发生器装置具有减少的抖动时钟相位
公开(公告)号：US20070164884A1
公开(公告)日：2007-07-19
申请号：US10596043
申请日：2004-11-26
申请人： Hassan Ihs
发明人： Hassan Ihs
IPC分类号： H03M3/00
CPC分类号： H03K5/133 , H03K5/06 , H03K2005/00097 , H03K2005/00293 , H03L7/0805 , H03L7/0812 , H03M3/372 , H03M3/424 , H03M3/438 , H03M3/458 , H03M3/50
摘要： Clock pulse generator apparatus comprising a clock pulse generator for generating a train of primary clock pulses having leading and trailing edges. A delay line produces a train of delayed clock pulses presenting delayed edges whose timing relative to corresponding edges of the primary clock pulses is defined by the delay line. A logic circuit produces a train of combined clock pulses presenting leading and trailing edges defined alternately by one of the delayed edges and the corresponding edge of the primary clock pulse, so that the combined clock pulses comprise active clock phases having widths defined by the delay line; the variability of the widths of the active clock phases is smaller than the variability of the positions of the leading and trailing edges of the primary clock pulses.
摘要翻译：时钟脉冲发生器装置包括用于产生具有前沿和后沿的主时钟脉冲串的时钟脉冲发生器。延迟线产生一系列延迟的时钟脉冲，呈现延迟的边沿，其相对于主时钟脉冲的相应边缘的定时由延迟线限定。逻辑电路产生一串组合的时钟脉冲，其显示由主时钟脉冲的延迟边缘和相应边缘中的一个交替地定义的前沿和后沿，使得组合的时钟脉冲包括具有由延迟线限定的宽度的有源时钟相位 ; 有源时钟相位的宽度的变化小于主时钟脉冲的前沿和后沿的位置的可变性。

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