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1. 发明授权

US5418896A Skew processing circuit and method of calculating a preset value for the same 失效
标题翻译：倾斜处理电路和计算预设值的方法相同
公开(公告)号：US5418896A
公开(公告)日：1995-05-23
申请号：US669628
申请日：1991-03-14
申请人： Hidechika Kumamoto , Haruo Yamamoto , Masaya Fujimoto , Tsukasa Matsushita
发明人： Hidechika Kumamoto , Haruo Yamamoto , Masaya Fujimoto , Tsukasa Matsushita
IPC分类号： G06T3/60 , H04N1/387 , G06T11/00
CPC分类号： G06T3/608 , H04N1/3878
摘要： A skew processing circuit 33 includes two line buffers, a skew processing type line buffer 331 and an original type line buffer 332, and a write/read control circuit 333 for controlling the two line buffers. The write/read control circuit 333 is a control circuit for writing a given image data in the line buffers 331, 332 in single lines and selectively reading the data written in the two line buffers 331, 332. When an image data is written in the original type line buffer 332, addressed are sequentially written from the head address 0. On the other hand, when the image data is written in the skew processing type line buffer 331, a write start address RH0 is determined in correspondence with a skew angle, and the write start address RH0 is shifted in each line to discard the head portion of the image data by specified dots (specified addresses). Thus, by controlling the writing of data in the two line buffers 331, 332 and reading data from them, an image in an arbitrary area can be processed into the skew with an arbitrary angle.
摘要翻译：歪斜处理电路33包括两条行缓冲器，歪斜处理型行缓冲器331和原始行行缓冲器332，以及用于控制两行缓冲器的写/读控制电路333。写入/读取控制电路333是用于将线路缓冲器331,332中的给定图像数据以单行写入并选择性地读取写入两行缓冲器331,332中的数据的控制电路。当将图像数据写入原始类型行缓冲器332，从头地址0顺序写入。另一方面，当图像数据被写入偏斜处理类型行缓冲器331时，写入开始地址RH0与斜角对应地确定，并且写入开始地址RH0在每行中移位，以通过指定的点（指定的地址）丢弃图像数据的头部。因此，通过控制两行缓冲器331,332中的数据的写入和从它们读取数据，任意区域中的图像可以被处理成任意角度的偏斜。

2. 发明授权

US5272546A Laser beam controller 失效
标题翻译：激光束控制器
公开(公告)号：US5272546A
公开(公告)日：1993-12-21
申请号：US664313
申请日：1991-03-04
申请人： Haruo Yamamoto , Akira Shimatani , Hidechika Kumamoto , Masaya Fujimoto , Tsukasa Matsushita
发明人： Haruo Yamamoto , Akira Shimatani , Hidechika Kumamoto , Masaya Fujimoto , Tsukasa Matsushita
IPC分类号： G02B26/10 , B41J2/44 , B41J2/47 , G06K15/12 , H03K5/00 , H03K5/13 , H03K7/08 , H04N1/036 , H04N1/405 , H04N1/40 , G01D15/00
CPC分类号： H03K5/131 , G06K15/1209 , H03K7/08 , H04N1/4056 , H03K2005/00234
摘要： A laser beam controller comprises a basic pulse signal generating circuit, a delay circuit, a delay control circuit, a pulse generating circuit and a laser beam generator. The basic pulse signal generating circuit generates periodically occurring basic pulse signal. The delay circuit delays the basic pulse signal. The delay control circuit controls the delay time of the basic pulse in the delay circuit according to image data. The pulse generating circuit generates an output pulse having a width corresponding to the delay time of the basic pulse signal. The laser beam generator generates a laser beam for a duration corresponding to the width of the output pulse by said pulse generating circuit. According to the controller, any desired gradation of a pixel of the image is desirably produced.

3. 发明授权

US5072310A IC card for image processor 失效
标题翻译：图像处理器IC卡
公开(公告)号：US5072310A
公开(公告)日：1991-12-10
申请号：US523344
申请日：1990-05-14
申请人： Haruo Yamamoto , Tsukasa Matsushita , Hidechika Kumamoto , Masaya Fujimoto
发明人： Haruo Yamamoto , Tsukasa Matsushita , Hidechika Kumamoto , Masaya Fujimoto
IPC分类号： B42D15/10 , G03G15/00 , G03G21/00 , G06K19/07 , H04N1/00 , H04N1/21 , H04N1/23 , H04N1/32
CPC分类号： G03G15/5066 , H04N1/00962 , H04N1/2104 , H04N1/2158 , H04N1/32561 , G03G2215/00092 , H04N1/00204 , H04N2201/0081 , H04N2201/0082
摘要： An integrated circuit (IC) card for use in an image processing machine, such as a digital copying machine. The IC card includes a first storage area for storing data for controlling said image processor and a second storage area for storing image data to be processed by said image processor.

4. 发明授权

US5041919A Image processing apparatus 失效
公开(公告)号：US5041919A
公开(公告)日：1991-08-20
申请号：US442820
申请日：1989-11-29
申请人： Haruo Yamamoto , Masaya Fujimoto , Shinobu Satonaka , Tsukasa Matsushita
发明人： Haruo Yamamoto , Masaya Fujimoto , Shinobu Satonaka , Tsukasa Matsushita
IPC分类号： H04N1/00 , H04N1/38
CPC分类号： H04N1/00702 , H04N1/00681 , H04N1/00708 , H04N1/00748 , H04N1/00753 , H04N1/00766 , H04N1/00769 , H04N1/38
摘要： An image processing apparatus wherein a document on a document support table and an optical system are moved relative to each other for scanning to read the image of the document as a density signal, and the read signal is processed as required, the apparatus comprising a document mat so colored that when the document support table is covered with the mat, the read signal represents an intermediate color, discriminating device for judging whether the density signal represents the intermediate color to produce a binary signal, a memory having a memory capacity of l/n based on the density signal, a write control for causing the binary signal to be written in the memory device in synchronism with the scanning movement, and apparatus for determining the size of the document from the contents of the memory device.

5. 发明授权

US5070412A Apparatus for generating an enlargement/reduction signal 失效
标题翻译：用于产生放大/缩小信号的装置
公开(公告)号：US5070412A
公开(公告)日：1991-12-03
申请号：US441255
申请日：1989-11-27
申请人： Hidechika Kumamoto , Tsukasa Matsushita
发明人： Hidechika Kumamoto , Tsukasa Matsushita
IPC分类号： B41J2/485 , G06T3/40 , G09G5/36 , H04N1/393
CPC分类号： H04N1/3935
摘要： An enlargement/reduction signal generating apparatus comprises means for generating basic clock pulses, means for generating frequency-divided clock pulses of different kinds, having the different frequencies by dividing the frequency of said basic clock pulses, means for generating selection signals to combine said clock pulses generated by said basic clock pulse generating means and said frequency-divided clock pulse generating means, whereby the ratio of said reading clock pulses to said writing clock pulses corresponds to a predetermined enlargement/reduction ratio, and means for making enlargement/reduction clock pulses by combining said basic clock pulses and said frequency-divided clock pulses in correspondence with said selection signals from said selection signal generating means and for outputting said enlargement/reduction clock pulses as said reading clock pulses or said writing clock pulses. The enlargement/reduction signal generating apparatus is an apparatus for generating reading clock pulses and writing clock pulses to enlarge or reduce the image of digital data stored in a storing means. The apparatus may be disposed in an image processing unit for processing image information. The image processing unit may be used as a unit which receives image information from an optical unit, enlarges or reduces the image information, and outputs the enlarged/reduced image information to an image forming part, in a copying machine having a scanner and a printer. The copying machine may be a digital copying machine having a laser unit.
摘要翻译：放大/缩小信号发生装置包括用于产生基本时钟脉冲的装置，用于产生不同种类的分频时钟脉冲的装置，具有通过划分所述基本时钟脉冲的频率而具有不同频率的装置，用于产生选择信号的装置，以组合所述时钟由所述基本时钟脉冲发生装置和所述分频时钟脉冲发生装置产生的脉冲，由此所述读取时钟脉冲与所述写入时钟脉冲的比率对应于预定的放大/缩小比率，以及用于进行放大/缩小时钟脉冲的装置通过将所述基本时钟脉冲和所述分频时钟脉冲对应于来自所述选择信号发生装置的所述选择信号组合，并输出所述放大/缩小时钟脉冲作为所述读取时钟脉冲或所述写入时钟脉冲。放大/缩小信号发生装置是用于产生读取时钟脉冲和写入时钟脉冲以放大或减少存储在存储装置中的数字数据的图像的装置。该装置可以设置在用于处理图像信息的图像处理单元中。图像处理单元可以用作从光学单元接收图像信息的单元，放大或缩小图像信息，并且在具有扫描仪和打印机的复印机中将放大/缩小图像信息输出到图像形成部分。复印机可以是具有激光单元的数字复印机。

6. 发明授权

US5016194A Image forming apparatus 失效
公开(公告)号：US5016194A
公开(公告)日：1991-05-14
申请号：US431931
申请日：1989-11-06
申请人： Tsukasa Matsushita , Hidechika Kumamoto
发明人： Tsukasa Matsushita , Hidechika Kumamoto
IPC分类号： B41J2/485 , H04N1/04 , H04N1/387 , H04N1/393
CPC分类号： H04N1/3871 , H04N1/393
摘要： In an image forming apparatus including a digital image processing device, an overlay memory stores predetermined image data. The image data stored in the overlay memory is read at a predetermined timing in a predetermined cycle and composite data is made from the image data and image data outputted from a line memory. Since the image data stored in the overlay memory is read at the predetermined timing in the predetermined cycle, various kinds of overlaid image which may include a space-magnified image can be made by arbitrarily selecting the timing and cycle for reading.

7. 发明授权

US07119508B2 Drive control device for direct current motor, rotation drive system for direct current motor and semiconductor integrated circuit for driving coil 失效
标题翻译：用于直流电动机的驱动控制装置，用于直流电动机的旋转驱动系统和用于驱动线圈的半导体集成电路
公开(公告)号：US07119508B2
公开(公告)日：2006-10-10
申请号：US10808531
申请日：2004-03-25
申请人： Minoru Kurosawa , Tsukasa Matsushita , Kunihiro Kawauchi
发明人： Minoru Kurosawa , Tsukasa Matsushita , Kunihiro Kawauchi
IPC分类号： H02K21/00 , H02K23/00 , H02K31/00 , H02P1/18 , H02P3/08
CPC分类号： G11B19/28 , H02M7/53875 , H02M2001/0009 , H02P6/28
摘要： A dc motor drive system with a PWM control system permits a high-accuracy rotation drive control while detecting the currents flowing into the coils without using shunt resistors. The system drives output MOS transistors by the PWM control to make the currents flow into the coils, and drives to rotate the dc motor. The system includes current sensing MOS transistors having a predetermined size ratio 1/m (M>1) to the output MOS transistors that make the currents flow into the coils. The current sensing MOS transistors are capable of making flow reduced currents proportional to the currents of the output MOS transistors.
摘要翻译：具有PWM控制系统的直流电机驱动系统允许高精度的旋转驱动控制，同时检测流入线圈的电流，而不使用分流电阻。该系统通过PWM控制驱动输出MOS晶体管，使电流流入线圈，并驱动直流电机旋转。该系统包括与使电流流入线圈的输出MOS晶体管具有预定尺寸比1 / m（M> 1）的电流感测MOS晶体管。电流感测MOS晶体管能够使流量减小的电流与输出MOS晶体管的电流成比例。

8. 发明申请

US20090068796A1 SEMICONDUCTOR CONNECTION COMPONENT 有权
标题翻译：半导体连接组件
公开(公告)号：US20090068796A1
公开(公告)日：2009-03-12
申请号：US12267079
申请日：2008-11-07
申请人： Nobuya Koike , Tsukasa Matsushita , Hiroshi Sato , Keiichi Okawa , Atsushi Nishikizawa
发明人： Nobuya Koike , Tsukasa Matsushita , Hiroshi Sato , Keiichi Okawa , Atsushi Nishikizawa
IPC分类号： H01L21/50
CPC分类号： H01L23/49524 , H01L23/4952 , H01L24/03 , H01L24/05 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/84 , H01L24/91 , H01L29/7816 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2224/37147 , H01L2224/40245 , H01L2224/45014 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/73221 , H01L2224/84801 , H01L2224/8485 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2924/00015 , H01L2924/207
摘要： There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.
摘要翻译：需要提供一种能够降低将功率晶体管和控制集成电路集成到单个半导体芯片的半导体器件中的功率晶体管的导通电阻的技术。另外需要提供能够减少半导体器件的芯片尺寸的技术。半导体芯片包括形成功率晶体管的功率晶体管形成区域，形成逻辑电路的逻辑电路形成区域和形成模拟电路的模拟电路形成区域。在功率晶体管形成区域中形成焊盘。焊盘和引线通过横截面大于导线的夹子连接。另一方面，焊盘通过导线29连接。

9. 发明授权

US5659402A Image processing method and apparatus 失效
标题翻译：图像处理方法和装置
公开(公告)号：US5659402A
公开(公告)日：1997-08-19
申请号：US367846
申请日：1995-01-03
申请人： Hiroyuki Fujita , Ariyoshi Hikosaka , Tetsuji Kajitani , Hidemitsu Hirano , Takuji Okumura , Tsukasa Matsushita , Hideo Azumai , Satoshi Iwatsubo
发明人： Hiroyuki Fujita , Ariyoshi Hikosaka , Tetsuji Kajitani , Hidemitsu Hirano , Takuji Okumura , Tsukasa Matsushita , Hideo Azumai , Satoshi Iwatsubo
IPC分类号： H04N1/40
CPC分类号： H04N1/40062
摘要： In accordance with the present invention, a quadratic differential values is first calculated, based on differences in the density data between an object pixel and respective peripheral pixels around the object pixel. The square value SS of the quadratic differential value S and the sum .SIGMA.SS obtained by adding up the square values SS of quadratic differential values for continuous five pixels are employed as determination values (step n1). The square sum .SIGMA.SS is compared with respective threshold values a, b and d, and the square value SS is compared with respective threshold values c, e and f (steps n2 to n6 and n8). Based on these comparison results, it is judged which image area among a character image area, gray-scale image area and dotted image area the object pixel belongs to. As for the image area judgement concerning the dotted image area, the final judgement that the object pixel belongs to the dotted image area is made only when nine continuous pixels including the object pixel are all judged to belong to the dotted image area. Since the square values SS and square sum .SIGMA.SS take only a positive value, the threshold values are set only in a positive range, and hence the image processing can be simplified. Further, by employing the square sum .SIGMA.SS, the states of the peripheral pixels can be taken into consideration for the image area judgement.
摘要翻译：根据本发明，首先基于对象像素与对象像素周围的相应周边像素之间的浓度数据的差异，首先计算二次微分值。采用二次微分值S的平方值SS和通过将连续5个像素的二次微分值的平方值SS相加得到的总和SIGMA SS作为确定值（步骤n1）。将平方和SIGMA SS与相应的阈值a，b和d进行比较，并将平方值SS与相应的阈值c，e和f进行比较（步骤n2至n6和n8）。基于这些比较结果，判断对象像素所属的字符图像区域，灰度图像区域和虚线图像区域中的哪个图像区域。对于关于虚线图像区域的图像区域判断，仅当包括对象像素的九个连续像素都被判断为属于虚线图像区域时，仅进行对象像素属于虚线图像区域的最终判断。由于平方值SS和平方和SIGMA SS仅取正值，所以仅在正的范围内设定阈值，因此能够简化图像处理。此外，通过采用平方和SIGMA SS，可以考虑周边像素的状态用于图像区域判断。

10. 发明授权

US08298859B2 Semiconductor connection component 失效
标题翻译：半导体连接组件
公开(公告)号：US08298859B2
公开(公告)日：2012-10-30
申请号：US13035273
申请日：2011-02-25
申请人： Nobuya Koike , Tsukasa Matsushita , Hiroshi Sato , Keiichi Okawa , Atsushi Nishikizawa
发明人： Nobuya Koike , Tsukasa Matsushita , Hiroshi Sato , Keiichi Okawa , Atsushi Nishikizawa
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/49524 , H01L23/4952 , H01L24/03 , H01L24/05 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/84 , H01L24/91 , H01L29/7816 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2224/37147 , H01L2224/40245 , H01L2224/45014 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/73221 , H01L2224/84801 , H01L2224/8485 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2924/00015 , H01L2924/207
摘要： There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire.
摘要翻译：需要提供一种能够降低将功率晶体管和控制集成电路集成到单个半导体芯片的半导体器件中的功率晶体管的导通电阻的技术。另外需要提供能够减少半导体器件的芯片尺寸的技术。半导体芯片包括形成功率晶体管的功率晶体管形成区域，形成逻辑电路的逻辑电路形成区域和形成模拟电路的模拟电路形成区域。在功率晶体管形成区域中形成焊盘。焊盘和引线通过横截面大于导线的夹子连接。另一方面，焊盘通过导线连接。

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