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1. 发明申请

US20090298254A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20090298254A1
公开(公告)日：2009-12-03
申请号：US12541457
申请日：2009-08-14
申请人： Haruhiko KOYAMA , Mitsuhiro Noguchi , Minori Kajimoto
发明人： Haruhiko KOYAMA , Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L21/30
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.
摘要翻译：在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。第一开口被配置为对准标记。第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。

2. 发明授权

US07585742B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07585742B2
公开(公告)日：2009-09-08
申请号：US11536291
申请日：2006-09-28
申请人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
发明人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.
摘要翻译：在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。第一开口被配置为对准标记。第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。

3. 发明申请

US20070077719A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20070077719A1
公开(公告)日：2007-04-05
申请号：US11536291
申请日：2006-09-28
申请人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
发明人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L21/331
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.
摘要翻译：在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。第一开口被配置为对准标记。第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。

4. 发明授权

US07943478B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07943478B2
公开(公告)日：2011-05-17
申请号：US12541457
申请日：2009-08-14
申请人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
发明人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.
摘要翻译：在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。第一开口被配置为对准标记。第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。

5. 发明授权

US08008703B2 Nonvolatile semiconductor memory device with twin-well 有权
标题翻译：具有双阱的非易失性半导体存储器件
公开(公告)号：US08008703B2
公开(公告)日：2011-08-30
申请号：US12175201
申请日：2008-07-17
申请人： Mitsuhiro Noguchi , Minori Kajimoto
发明人： Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L29/788
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526
摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.
摘要翻译：非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离，其形成在半导体衬底中。第三井具有比第二井的第二部分更少的深度。

6. 发明授权

US07781823B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07781823B2
公开(公告)日：2010-08-24
申请号：US12457704
申请日：2009-06-18
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/7881 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.
摘要翻译：根据本发明的非易失性半导体存储器包括：存储单元单元，其包括彼此并联形成的数据选择线，与数据选择线相交并且彼此并联排列的数据传输线;以及电可重写存储单元晶体管，数据传输线和数据选择线的交点。它还包括：存储单元阵列块，其中存储单元单元沿数据选择线设置; 第一源极线，连接到存储单元单元的一端，并沿数据选择线对齐; 以及第二源极线，其电连接到第一源极线，并且沿着数据选择线设置。

7. 发明申请

US20100052032A1 Nonvolatile semiconductor memory and method for fabricating the same 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20100052032A1
公开(公告)日：2010-03-04
申请号：US12588203
申请日：2009-10-07
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

8. 发明授权

US07622762B2 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07622762B2
公开(公告)日：2009-11-24
申请号：US12000396
申请日：2007-12-12
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

9. 发明授权

US08377720B2 Method of manufacturing a semiconductor device including an insulating film beside an element isolation film 失效
标题翻译：制造包括元件隔离膜旁边的绝缘膜的半导体器件的方法
公开(公告)号：US08377720B2
公开(公告)日：2013-02-19
申请号：US11419079
申请日：2006-05-18
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroyuki Nitta
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroyuki Nitta
IPC分类号： H01L21/00
CPC分类号： H01L27/088 , H01L21/823857 , H01L21/823892 , H01L27/0207 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed.
摘要翻译：半导体器件的制造方法包括在半导体衬底上形成不同厚度的栅极绝缘膜的工艺，沉积构成栅电极的膜，去除在包括晶体管的晶体管的杂质扩散区域表面上形成的具有不同厚度的栅极绝缘膜栅极电极和将杂质掺杂到去除栅极绝缘膜的部分中。

10. 发明申请

US20050051831A1 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050051831A1
公开(公告)日：2005-03-10
申请号：US10890132
申请日：2004-07-14
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

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