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1. 发明授权

US07231533B2 Wake-up reset circuit draws no current when a control signal indicates sleep mode for a digital device 有权
标题翻译：当控制信号表示数字设备的睡眠模式时，唤醒复位电路不会消耗电流
公开(公告)号：US07231533B2
公开(公告)日：2007-06-12
申请号：US10924488
申请日：2004-08-24
申请人： Hartono Darmawaskita , Layton Eagar , Ryan Scott Ellison , Vivien Delport
发明人： Hartono Darmawaskita , Layton Eagar , Ryan Scott Ellison , Vivien Delport
IPC分类号： G06F1/26
CPC分类号： G06F1/24
摘要： A wake-up reset circuit is provided that generates a reset signal to a digital circuit upon a wake-up event. The wake-up reset circuit places the digital circuit into a known reset condition upon wake-up, even if a brown out condition occurs which may have caused unstable and unknown logic states in sequential circuit elements, e.g., volatile memory, flip flops and/or latching circuits. The wake-up reset circuit draws substantially no current when not generating the reset signal.
摘要翻译：提供唤醒复位电路，其在唤醒事件时向数字电路产生复位信号。唤醒复位电路在唤醒时将数字电路置于已知的复位状态，即使发生了可能在顺序电路元件中出现不稳定和未知逻辑状态的欠压状态，例如易失性存储器，触发器和/ 或锁存电路。当不产生复位信号时，唤醒复位电路基本上不消耗电流。

2. 发明授权

US06515464B1 Input voltage offset calibration of an analog device using a microcontroller 有权
标题翻译：使用微控制器的模拟设备的输入电压失调校准
公开(公告)号：US06515464B1
公开(公告)日：2003-02-04
申请号：US09675356
申请日：2000-09-29
申请人： Hartono Darmawaskita , Layton Eagar , Miguel Moreno
发明人： Hartono Darmawaskita , Layton Eagar , Miguel Moreno
IPC分类号： G01R1900
CPC分类号： H03M1/1019 , H03F3/45977 , H03M1/12
摘要： Input offset voltage calibration of an analog device, or plurality of analog devices, is controlled by a microcontroller. The microcontroller and analog device(s) are fabricated on an integrated circuit die or in a multi-chip package. The microcontroller applies a digital word to an input offset voltage compensation circuit of the analog device for generating input offset voltage compensation. The analog device is switched to a calibrate mode and a voltage comparator compares the output of the analog input device and a voltage reference. When the output of the analog input device is equal to or greater than the voltage reference, the comparator output signals the microcontroller by changing its output logic level. The input offset voltage compensation circuit of the analog input device has a storage register or memory that retains the digital word which compensates for the input offset voltage.
摘要翻译：模拟设备或多个模拟设备的输入偏移电压校准由微控制器控制。微控制器和模拟设备在集成电路管芯或多芯片封装中制造。微控制器将数字字应用于模拟装置的输入失调电压补偿电路，用于产生输入失调电压补偿。模拟设备切换到校准模式，电压比较器比较模拟输入设备的输出和电压参考。当模拟输入装置的输出等于或大于参考电压时，比较器输出通过改变其输出逻辑电平来发出信号。模拟输入设备的输入失调电压补偿电路具有保存数字字的存储寄存器或存储器，用于补偿输入失调电压。

3. 发明授权

US06459335B1 Auto-calibration circuit to minimize input offset voltage in an integrated circuit analog input device 有权
标题翻译：自动校准电路，以最小化集成电路模拟输入设备中的输入失调电压
公开(公告)号：US06459335B1
公开(公告)日：2002-10-01
申请号：US09676389
申请日：2000-09-29
申请人： Hartono Darmawaskita , Layton Eagar , Miguel Moreno
发明人： Hartono Darmawaskita , Layton Eagar , Miguel Moreno
IPC分类号： H03F114
CPC分类号： H03M1/1019 , H03F3/45977 , H03M1/12
摘要： An auto-calibration circuit minimizes input offset voltage in an integrated circuit analog input device. The auto-calibration circuit may also calibrate a plurality of analog input devices on an integrated circuit die or in a multi-chip package (MCP). The auto-calibration circuit and analog input device(s) may be fabricated in combination with a microcontroller system on an integrated circuit die or in an MCP. The auto-calibration circuit controls input offset voltage compensation circuit that counteracts or compensates for input offset voltage so as to minimize voltage error at the output of the analog input device. A digital control circuit applies a digital word to the input offset voltage compensation circuit for generating the required input offset voltage compensation. A linear search or binary search of various values of the digital word may be used by the digital control circuit. The digital control circuit switches the inputs, the output and feedback-gain determining resistors for the analog input device during a calibration mode. A voltage comparator compares the output of the analog input device and a voltage reference. When the output of the analog input device is equal to or greater than the voltage reference, the comparator output signals the digital control circuit by changing its output logic level. The input offset voltage compensation circuit of the analog input device has a storage register or memory that retains the digital word which compensates for the input offset voltage.
摘要翻译：自动校准电路使集成电路模拟输入设备中的输入失调电压最小化。自动校准电路还可以校准集成电路管芯上或多芯片封装（MCP）中的多个模拟输入设备。自动校准电路和模拟输入设备可以与集成电路管芯或MCP中的微控制器系统组合制造。自动校准电路控制抵消或补偿输入失调电压的输入失调电压补偿电路，以最小化模拟输入设备输出端的电压误差。数字控制电路将数字字应用于输入偏移电压补偿电路，以产生所需的输入失调电压补偿。可以由数字控制电路使用数字字的各种值的线性搜索或二进制搜索。数字控制电路在校准模式期间切换模拟输入设备的输入，输出和反馈增益确定电阻。电压比较器比较模拟输入装置的输出和电压基准。当模拟输入装置的输出等于或大于参考电压时，比较器输出通过改变其输出逻辑电平来向数字控制电路发出信号。模拟输入设备的输入失调电压补偿电路具有保存数字字的存储寄存器或存储器，用于补偿输入失调电压。

4. 发明申请

US20050138454A1 Wake-up reset circuit 有权
标题翻译：唤醒复位电路
公开(公告)号：US20050138454A1
公开(公告)日：2005-06-23
申请号：US10924488
申请日：2004-08-24
申请人： Hartono Darmawaskita , Layton Eagar , Ryan Ellison , Vivien Delport
发明人： Hartono Darmawaskita , Layton Eagar , Ryan Ellison , Vivien Delport
IPC分类号： G06F1/24 , H03K17/22 , G06F1/26
CPC分类号： G06F1/24
摘要： A wake-up reset circuit is provided that generates a reset signal to a digital circuit upon a wake-up event. The wake-up reset circuit places the digital circuit into a known reset condition upon wake-up, even if a brown out condition occurs which may have caused unstable and unknown logic states in sequential circuit elements, e.g., volatile memory, flip flops and/or latching circuits. The wake-up reset circuit draws substantially no current when not generating the reset signal.
摘要翻译：提供唤醒复位电路，其在唤醒事件时向数字电路产生复位信号。唤醒复位电路在唤醒时将数字电路置于已知的复位状态，即使发生了可能在顺序电路元件中出现不稳定和未知逻辑状态的欠压状态，例如易失性存储器，触发器和/ 或锁存电路。当不产生复位信号时，唤醒复位电路基本上不消耗电流。

5. 发明授权

US06535061B2 Configurable operational amplifier as a microcontroller peripheral 有权
公开(公告)号：US06535061B2
公开(公告)日：2003-03-18
申请号：US09731381
申请日：2000-12-06
申请人： Hartono Darmawaskita , Layton Eagar
发明人： Hartono Darmawaskita , Layton Eagar
IPC分类号： H03F345
CPC分类号： H03K5/2472 , G06F15/7814 , Y02D10/12 , Y02D10/13
摘要： A configurable operational amplifier which is programmed to specific characteristics and parameters for various requirements in the measurement of analog signals. These programmable characteristics and parameters are gain bandwidth product (GBWP), selection of operational amplifier (op-amp) or comparator modes of operation, input offset zero calibration, ultra low input bias current, rail-to-rail input operation, and rail-to-rail output operation. The configurable operational amplifier is used in combination with a microcontroller system, and may be fabricated on an integrated circuit die or in a multi-chip package.

6. 发明授权

US5899570A Time-based temperature sensor system and method therefor 失效
标题翻译：基于时间的温度传感器系统及其方法
公开(公告)号：US5899570A
公开(公告)日：1999-05-04
申请号：US827516
申请日：1997-03-28
申请人： Hartono Darmawaskita , James B. Nolan
发明人： Hartono Darmawaskita , James B. Nolan
IPC分类号： G01K7/20 , G01K7/00
CPC分类号： G01K7/203
摘要： A time-based digital temperature sensing system has a first oscillator which is temperature sensitive. The first oscillator has a temperature coefficient which allows the first oscillator to generate an output signal which varies linearly as a function of temperature. A second oscillator is provided and is used to generates a reference clock signal. The outputs from the first and the second oscillator are coupled to a timer. The timer has a clock input coupled to an output of the second oscillator and an enable input coupled to an output of the first oscillator. From these input signals, the timer generates a number indicative of a length of time the timer is enabled by the first oscillator. The number is proportional to a current temperature of a material that is being monitored by the temperature sensing system.
摘要翻译：基于时间的数字温度感测系统具有温度敏感的第一振荡器。第一振荡器具有允许第一振荡器产生作为温度的函数线性变化的输出信号的温度系数。提供了第二个振荡器，用于产生一个参考时钟信号。来自第一和第二振荡器的输出耦合到定时器。定时器具有耦合到第二振荡器的输出的时钟输入和耦合到第一振荡器的输出的使能输入。从这些输入信号中，定时器产生指示定时器由第一振荡器使能的时间长度的数字。该数量与由温度感测系统监测的材料的当前温度成比例。

7. 发明授权

US5854564A Direct sensor interface (DSI) module 失效
标题翻译：直接传感器接口（DSI）模块
公开(公告)号：US5854564A
公开(公告)日：1998-12-29
申请号：US855868
申请日：1997-05-12
申请人： Hartono Darmawaskita , James B. Nolan
发明人： Hartono Darmawaskita , James B. Nolan
IPC分类号： G01R27/02 , G01R27/26 , H03K5/153 , H03K5/22
CPC分类号： H03K5/153
摘要： A direct sensor interface (DSI) module which allows a microcontroller to directly interface to sensors having at least one of a resistive, capacitive, and/or current source characteristic. The DSI module is coupled directly to a sensor device, which could be a reference resistor, which generates a sensor current. A current mirroring circuit outputs a charging current proportional to the sensor current. A capacitive sensor and/or a capacitive device is coupled to the current mirroring circuit and generates a voltage when charged by the charging current. Using a comparator and a threshold voltage source, the time it takes the capacitive sensor and/or a capacitive device to ramp up from zero to the threshold voltage can be measured. The charging time is proportional to the sensor reading.
摘要翻译：直接传感器接口（DSI）模块，其允许微控制器直接与具有电阻，电容和/或电流源特性中的至少一个的传感器接口。 DSI模块直接耦合到传感器设备，传感器设备可以是参考电阻器，可以产生传感器电流。电流镜像电路输出与传感器电流成比例的充电电流。电容式传感器和/或电容性装置耦合到电流镜像电路，并且当由充电电流充电时产生电压。使用比较器和阈值电压源，可以测量电容传感器和/或电容器件从零上升到阈值电压所花费的时间。充电时间与传感器读数成正比。

8. 发明授权

US08487685B2 Enhanced complementary waveform generator 有权
标题翻译：增强互补波形发生器
公开(公告)号：US08487685B2
公开(公告)日：2013-07-16
申请号：US13435642
申请日：2012-03-30
申请人： Sean Steedman , Hartono Darmawaskita , Stephen Bowling , Cristian Groza , Ward Brown , Zacharias Martin Smit
发明人： Sean Steedman , Hartono Darmawaskita , Stephen Bowling , Cristian Groza , Ward Brown , Zacharias Martin Smit
IPC分类号： H03K3/00
CPC分类号： H03K7/08
摘要： An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.
摘要翻译：增强型互补波形发生器（ECWG）产生由上升和下降事件源确定的两个互补脉宽调制（PWM）输出。在ECWG的简单配置中，上升和下降事件源是具有期望周期和占空比的PWM信号相同的信号。 ECWG将该单个PWM输入转换为双互补PWM输出。双PWM输出的频率和占空比基本上与单输入PWM信号的频率和占空比相匹配。在双互补PWM输出之间可能引入消隐和死区时间，双互补PWM输出也可能是相位延迟的。

9. 发明申请

US20130057330A1 ENHANCED COMPLEMENTARY WAVEFORM GENERATOR 有权
标题翻译：增强型补充波形发生器
公开(公告)号：US20130057330A1
公开(公告)日：2013-03-07
申请号：US13435642
申请日：2012-03-30
申请人： Sean Steedman , Hartono Darmawaskita , Stephen Bowling , Cristian Groza , Ward Brown , Zacharias Martin Smit
发明人： Sean Steedman , Hartono Darmawaskita , Stephen Bowling , Cristian Groza , Ward Brown , Zacharias Martin Smit
IPC分类号： H03K3/01
CPC分类号： H03K7/08
摘要： An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.
摘要翻译：增强型互补波形发生器（ECWG）产生由上升和下降事件源确定的两个互补脉宽调制（PWM）输出。在ECWG的简单配置中，上升和下降事件源是具有期望周期和占空比的PWM信号相同的信号。 ECWG将该单个PWM输入转换为双互补PWM输出。双PWM输出的频率和占空比基本上与单输入PWM信号的频率和占空比相匹配。在双互补PWM输出之间可能引入消隐和死区时间，双互补PWM输出也可能是相位延迟的。

10. 发明授权

US07644217B2 Detecting connection to a USB host or hub without using an extra status input 有权
标题翻译：检测到USB主机或集线器的连接，而不使用额外的状态输入
公开(公告)号：US07644217B2
公开(公告)日：2010-01-05
申请号：US11681253
申请日：2007-03-02
申请人： Daniel Butler , Hartono Darmawaskita
发明人： Daniel Butler , Hartono Darmawaskita
IPC分类号： G06F13/00 , G06F13/42 , H03K17/16 , G06F13/14
CPC分类号： G06F13/4081 , G06F1/3203 , G06F1/3253 , G06F2213/0042 , Y02D10/151 , Y02D50/20
摘要： A low power Universal Serial Bus (USB) capable device uses a weak pull-up resistance that is coupled to at least one data line of the USB for detection of when the USB capable device is connected to a USB host or hub. When the USB capable device is not connected to the USB host or hub, USB peripheral, including the USB transceiver, USB voltage regulator, serial interface and/or USB logic circuits required for USB operation may be powered down to conserve power drawn by the USB capable device. When the USB capable device is connected to the USB host or hub, a voltage from the weak pull-up will be significantly reduced, thus signaling that the USB peripheral and associated circuits should be powered up for normal USB operation.
摘要翻译：低功率通用串行总线（USB）能力的设备使用弱上拉电阻，其耦合到USB的至少一个数据线，用于检测USB能力设备何时连接到USB主机或集线器。当USB设备未连接到USB主机或集线器时，USB外围设备（包括USB收发器，USB电压调节器，串行接口和/或USB操作所需的USB逻辑电路）可能会关闭电源，以节省由USB 有能力的设备。当USB设备连接到USB主机或集线器时，弱上拉电压将显着降低，从而表明USB外设和相关电路应通电以进行正常的USB操作。

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