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1. 发明申请

US20120284548A1 Zero Indication Forwarding for Floating Point Unit Power Reduction 失效
标题翻译：浮点单元功率降低的零指示转发
公开(公告)号：US20120284548A1
公开(公告)日：2012-11-08
申请号：US13552327
申请日：2012-07-18
申请人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
发明人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译：一种在处理数学运算时降低功耗的方法和系统。在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。当至少一个操作数为零操作数或至少一个操作数无序时，会设置一个触发门控时钟信号的标志。时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。

2. 发明授权

US08578196B2 Zero indication forwarding for floating point unit power reduction 失效
标题翻译：用于浮点单元功率降低的零指示转发
公开(公告)号：US08578196B2
公开(公告)日：2013-11-05
申请号：US13552327
申请日：2012-07-18
申请人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
发明人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译：一种在处理数学运算时降低功耗的方法和系统。在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。

3. 发明授权

US08255726B2 Zero indication forwarding for floating point unit power reduction 失效
标题翻译：用于浮点单元功率降低的零指示转发
公开(公告)号：US08255726B2
公开(公告)日：2012-08-28
申请号：US12176191
申请日：2008-07-18
申请人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
发明人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method, system and computer program product for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译：一种用于在处理数学运算时降低功耗的方法，系统和计算机程序产品。在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。

4. 发明申请

US20090198758A1 METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER 审中-公开
标题翻译：多精度乘法器中的符号扩展方法
公开(公告)号：US20090198758A1
公开(公告)日：2009-08-06
申请号：US12023072
申请日：2008-01-31
申请人： Harry S. Barowski , Jeffrey Adam Butts , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
发明人： Harry S. Barowski , Jeffrey Adam Butts , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
IPC分类号： G06F7/496
CPC分类号： G06F7/49994 , G06F7/523 , G06F7/5318 , G06F7/5332 , G06F7/5443
摘要： A method for implementing sign extension within a multi-precision multiplier is described. The method includes receiving a first input within a multiplier core of the multiplier, receiving a second input within the multiplier core, and creating partial products in the multiplier core using the first and second inputs. The method also includes summing up the partial products in a partial product reduction tree in the multiplier core. The method also includes performing sign extension within the partial product reduction tree of the multiplier core by adding a value to a partial product of the partial product reduction tree. The method further includes computing an output from the partial product reduction tree, the output including a final product of the first and second inputs signed extended to a desired width.
摘要翻译：描述了一种在多精度乘法器内实现符号扩展的方法。该方法包括：在乘法器的乘法器核心内接收第一输入，接收乘法器内核中的第二输入，以及使用第一和第二输入在乘法器内核中产生部分乘积。该方法还包括在乘法器核心中的部分乘积减少树中总结部分乘积。该方法还包括通过向部分乘积减少树的部分乘积添加值来在乘法器核心的部分乘积减少树内执行符号扩展。该方法还包括计算来自部分乘积减少树的输出，该输出包括被扩展到期望宽度的第一和第二输入的最终产品。

5. 发明申请

US20100063987A1 SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR 有权
标题翻译：支持浮点处理器中的多个格式
公开(公告)号：US20100063987A1
公开(公告)日：2010-03-11
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译：在二进制浮点处理器中，通过使用结果精度（“Emin”）的最小指数值偏移指数，即将重新编码的值转换为内部格式，将各种类型的操作数中的每一个的指数重新编码为内部格式指数是指数减去Emin的表示值。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。然后以这种新格式执行指数计算。对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。

6. 发明授权

US08291003B2 Supporting multiple formats in a floating point processor 有权
标题翻译：在浮点处理器中支持多种格式
公开(公告)号：US08291003B2
公开(公告)日：2012-10-16
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译：在二进制浮点处理器中，通过用结果精度（Emin）的最小指数值偏置指数，将各种类型的操作数中的每一个的指数重新编码为内部格式，即指数的重新编码值为指数的代表值减去Emin。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。然后以这种新格式执行指数计算。对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。

7. 发明授权

US08407275B2 Fast floating point compare with slower backup for corner cases 有权
标题翻译：快速浮点与较慢的备份角落比较
公开(公告)号：US08407275B2
公开(公告)日：2013-03-26
申请号：US12255968
申请日：2008-10-22
申请人： Maarten J. Boersma , Michael Kroener , Silvia M. Mueller , Jochen Preiss
发明人： Maarten J. Boersma , Michael Kroener , Silvia M. Mueller , Jochen Preiss
IPC分类号： G06F7/02
CPC分类号： G06F9/30021 , G06F9/30025
摘要： A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail.
摘要翻译：浮点处理器单元通过比较整数格式的两个操作数来执行具有相同或不同精度的两个操作数的浮点比较指令，这显着地加快了浮点比较指令的执行。浮点处理器现在对于几乎大多数操作数情况（例如，所有情况的99％），至少执行两倍快或更快（例如，现有技术中的两个时钟周期而不是五个时钟周期）的浮点比较指令。只有罕见的角落情况需要在其中一个操作数上进行额外的操作，因此需要额外的执行周期，因为整数比较操作将不适用于这些角色。这是由于一个操作数是非正规化表示中的单精度子正规数（即，具有两个表示），另一个操作数处于SP子正常范围，使得整数比较操作将失败。

8. 发明申请

US20100023573A1 EFFICIENT FORCING OF CORNER CASES IN A FLOATING POINT ROUNDER 有权
标题翻译：在浮动点圆环中有效地施加拐角
公开(公告)号：US20100023573A1
公开(公告)日：2010-01-28
申请号：US12177346
申请日：2008-07-22
申请人： Maarten J. Boersma , J. Adam Butts , Silvia M. Mueller , Jochen Preiss
发明人： Maarten J. Boersma , J. Adam Butts , Silvia M. Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/49947
摘要： The forcing of the result or output of a rounder portion of a floating point processor occurs only in a fraction non-increment data path within the rounder and not in the fraction increment data path within the rounder. The fraction forcing is active on a corner case such as a disabled overflow exception. A disabled overflow exception may be detected by inspecting the normalized exponent. If a disabled overflow exception is detected, the round mode is selected to execute only in the non-increment data path thereby preventing the fraction increment data path from being selected.
摘要翻译：强制浮点处理器的较圆形部分的结果或输出仅在舍入器内的分数非递增数据路径中发生，而不在舍入器内的分数增量数据路径中。部分强制在角落外部活动，例如禁用的溢出异常。可以通过检查归一化指数来检测到禁用的溢出异常。如果检测到禁用的溢出异常，则选择循环模式仅在非增量数据路径中执行，从而防止分数增量数据路径被选择。

9. 发明申请

US20090198974A1 METHODS FOR CONFLICT-FREE, COOPERATIVE EXECUTION OF COMPUTATIONAL PRIMITIVES ON MULTIPLE EXECUTION UNITS 失效
标题翻译：无冲突的方法，多个执行单位的计算原则的合作执行
公开(公告)号：US20090198974A1
公开(公告)日：2009-08-06
申请号：US12023432
申请日：2008-01-31
申请人： Harry S. Barowski , J. Adam Butts , Stephen V. Kosonocky , Silvia M. Mueller , Jochen Preiss
发明人： Harry S. Barowski , J. Adam Butts , Stephen V. Kosonocky , Silvia M. Mueller , Jochen Preiss
IPC分类号： G06F9/44 , G06F17/11
CPC分类号： G06F7/57 , G06F7/49921 , G06F9/30014 , G06F9/3893
摘要： A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit.
摘要翻译：根据示例性实施例提供了一种用于执行多个计算原语的方法。第一计算单元和至少第二计算单元合作执行多个计算原语。第一计算单元独立计算其他计算原语。通过对共享源操作数总线或共享结果总线的仲裁，通过协作地执行多个计算原语所需的第一和第二计算单元的可用性通过用于在专用计算单元上执行的计算原语的预留处理来确保。

10. 发明授权

US07694112B2 Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation 失效
标题翻译：来自第二执行单元的多路复用输出用于复合计算的第一原始执行单元的较宽宽度中间结果的添加/饱和处理部分
公开(公告)号：US07694112B2
公开(公告)日：2010-04-06
申请号：US12023432
申请日：2008-01-31
申请人： Harry S. Barowski , J. Adam Butts , Stephen V. Kosonocky , Silvia M. Mueller , Jochen Preiss
发明人： Harry S. Barowski , J. Adam Butts , Stephen V. Kosonocky , Silvia M. Mueller , Jochen Preiss
IPC分类号： G06F9/302
CPC分类号： G06F7/57 , G06F7/49921 , G06F9/30014 , G06F9/3893
摘要： A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit.
摘要翻译：根据示例性实施例提供了一种用于执行多个计算原语的方法。第一计算单元和至少第二计算单元合作执行多个计算原语。第一计算单元独立计算其他计算原语。通过对共享源操作数总线或共享结果总线的仲裁，通过协作地执行多个计算原语所需的第一和第二计算单元的可用性通过用于在专用计算单元上执行的计算原语的预留处理来确保。

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