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1. 发明申请

US20100065921A1 SEMICONDUCTOR DEVICE WITH LOCAL INTERCONNECTS 有权
标题翻译：具有本地互连的半导体器件
公开(公告)号：US20100065921A1
公开(公告)日：2010-03-18
申请号：US12212034
申请日：2008-09-17
申请人： Harry CHUANG , Kong-Beng THEI , Sheng-Chen CHUNG , Mong-Song LIANG
发明人： Harry CHUANG , Kong-Beng THEI , Sheng-Chen CHUNG , Mong-Song LIANG
IPC分类号： H01L29/78
CPC分类号： H01L21/76895 , H01L21/823475 , H01L27/088 , H01L29/4238
摘要： A semiconductor device with local interconnects is provided. The semiconductor device comprises a first gate line structure and a second gate line structure disposed on a substrate and substantially collinear. A first pair of source/drain regions is formed in the substrate on both sides of the first gate line structure and a second pair of source/drain regions is formed in the substrate on both sides of the second gate line structure. A pair of conductive lines is disposed on the substrate on both sides of the first gate line structure and the second gate line structure, such that each conductive line is connected to one of the first pair of source/drain regions and one of the second pair of source/drain regions.
摘要翻译：提供具有局部互连的半导体器件。半导体器件包括设置在衬底上并基本上共线的第一栅极线结构和第二栅极线结构。第一对源极/漏极区域形成在第一栅极线结构的两侧的衬底中，并且第二对源极/漏极区域形成在第二栅极线结构的两侧的衬底中。一对导线设置在第一栅极线结构和第二栅极线结构的两侧上的衬底上，使得每个导线连接到第一对源极/漏极区域中的一个并且第二对中的一个的源/漏区。

2. 发明申请

US20100087038A1 METHOD FOR N/P PATTERNING IN A GATE LAST PROCESS 有权
标题翻译：用于门窗最后过程中N / P图案的方法
公开(公告)号：US20100087038A1
公开(公告)日：2010-04-08
申请号：US12364384
申请日：2009-02-02
申请人： Sheng-Chen CHUNG , Kong-Beng THEI , Harry CHUANG
发明人： Sheng-Chen CHUNG , Kong-Beng THEI , Harry CHUANG
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/28088 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A method is provided that includes providing a substrate, forming a first gate structure in a first region and a second gate structure in a second region, the first and second gate structures each including a high-k dielectric layer, a silicon layer, and a hard mask layer, where the silicon layer of the first gate structure has a different thickness than the silicon layer of the second gate structure, forming an interlayer dielectric (ILD) over the first and second gate structures, performing a chemical mechanical polishing (CMP) on the ILD, removing the silicon layer from the first gate structure thereby forming a first trench, forming a first metal layer to fill in the first trench, removing the hard mask layer and the silicon layer from the second gate structure thereby forming a second trench, and forming a second metal layer to fill in the second trench.
摘要翻译：提供了一种方法，其包括提供衬底，在第一区域中形成第一栅极结构和在第二区域中形成第二栅极结构，所述第一和第二栅极结构各自包括高k电介质层，硅层和硬掩模层，其中第一栅极结构的硅层具有与第二栅极结构的硅层不同的厚度，在第一和第二栅极结构上形成层间电介质（ILD），执行化学机械抛光（CMP）在所述ILD上，从所述第一栅极结构去除所述硅层，从而形成第一沟槽，形成第一金属层以填充所述第一沟槽，从所述第二栅极结构去除所述硬掩模层和所述硅层，由此形成第二沟槽并且形成第二金属层以填充第二沟槽。

3. 发明申请

US20100087056A1 METHOD FOR GATE HEIGHT CONTROL IN A GATE LAST PROCESS 有权
标题翻译：门窗高度控制方法
公开(公告)号：US20100087056A1
公开(公告)日：2010-04-08
申请号：US12489053
申请日：2009-06-22
申请人： Sheng-Chen CHUNG , Kong-Beng THEI , Harry CHUANG
发明人： Sheng-Chen CHUNG , Kong-Beng THEI , Harry CHUANG
IPC分类号： H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate, forming a transistor in the substrate, the transistor having a gate structure that includes a dummy gate structure, forming an inter-layer dielectric (ILD), performing a first chemical mechanical polishing (CMP) to expose a top surface of the dummy gate structure, removing a portion of the ILD such that a top surface of the ILD is at a distance below the top surface of the dummy gate structure, forming a material layer over the ILD and dummy gate structure, performing a second CMP on the material layer to expose the top surface of the dummy gate structure, removing the dummy gate structure thereby forming a trench, forming a metal layer to fill in the trench, and performing a third CMP that substantially stops at the top surface of the ILD.
摘要翻译：提供了一种用于制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底中形成晶体管，晶体管具有包括虚拟栅极结构的栅极结构，形成层间电介质（ILD），执行第一化学机械抛光（CMP）以暴露伪栅极结构的顶表面，去除ILD的一部分，使得ILD的顶表面在虚拟栅极结构的顶表面下方的距离处，形成在 ILD和虚拟栅极结构，在材料层上执行第二CMP以暴露虚拟栅极结构的顶表面，去除伪栅极结构从而形成沟槽，形成金属层以填充沟槽，以及执行第三CMP 其基本上停留在ILD的顶表面。

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