专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4761783A Apparatus and method for reporting occurrences of errors in signals stored in a data processor 失效
标题翻译：用于报告存储在数据处理器中的信号中出现错误的装置和方法
公开(公告)号：US4761783A
公开(公告)日：1988-08-02
申请号：US920522
申请日：1986-10-17
申请人： Harold F. Christensen , Joseph A. Petolino, Jr.
发明人： Harold F. Christensen , Joseph A. Petolino, Jr.
IPC分类号： G06F11/07 , G06F11/10 , G06F12/00
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/10 , G06F12/00
摘要： The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first circuitry for storing multiple digital first signals; second circuitry for storing the multiple digital first signals and adapted for storing at least one digital second signal; third circuitry for transmitting the multiple digital first signals substantially from the first circuitry to the second circuitry; fourth circuitry for providing the at least one digital second signal, in the course of the transmitting of the first signals by the third circuitry, in response to an occurrence of one or more errors in one or more of the multiple digital first signals; fifth circuitry for transmitting the multiple digital first signals substantially from the second circuitry to the first means; and sixth circuitry adapted for receiving the at least one digital second signal in the course of the transmitting of the multiple digital first signals by the fifth circuitry and for providing at least one third signal in response to an occurrence of the at least one digital second signal.
摘要翻译：本发明提供一种用于报告存储在数据处理器的存储装置中的数据错误的装置，包括：用于存储多个数字第一信号的第一电路; 第二电路，用于存储多个数字第一信号并适于存储至少一个数字第二信号; 用于将所述多个数字第一信号基本上从所述第一电路传输到所述第二电路的第三电路; 第四电路，用于响应于多个数字第一信号中的一个或多个中的一个或多个错误的发生，在第三电路发送第一信号的过程中提供至少一个数字第二信号; 用于将所述多个数字第一信号基本上从所述第二电路传输到所述第一装置的第五电路; 以及第六电路，适于在第五电路发送多个数字第一信号的过程中接收至少一个数字第二信号，并响应于至少一个数字第二信号的出现而提供至少一个第三信号。

2. 发明授权

US4852100A Error detection and correction scheme for main storage unit 失效
标题翻译：主存储单元的错误检测和纠正方案
公开(公告)号：US4852100A
公开(公告)日：1989-07-25
申请号：US61847
申请日：1987-06-11
申请人： Harold F. Christensen , Jeffrey A. Thomas , Jeffrey Isozaki , Joseph A. Petolino
发明人： Harold F. Christensen , Jeffrey A. Thomas , Jeffrey Isozaki , Joseph A. Petolino
IPC分类号： G06F11/07 , G06F11/10 , G06F12/00
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/10 , G06F12/00
摘要： The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting said multiple digital first signals substantially from said first means to said second means; fourth means for providing said at least one digital second signal, in the course of the transmitting of said first signals by said third means, in response to an occurrence of one or more errors in one or more of said multiple digital first signals; fifth means for transmitting said multiple digital first signals substantially from said second means to said first means; and sixth means adapted for receiving said at least one digital second signal in the course of the transmitting of said multiple digital first signals by said fifth means and for providing at least one third signal in response to an occurrence of said at least one digital second signal. ECC codes are generated and applied over a plurality of distinct checking blocks in each flow of data in order to minimize delays in the move-in data path, and bypass data paths are provided such that a flow may bypass all error checking and correcting circuitry and cacheing apparatus between the main storage array and the CPU.
摘要翻译：本发明提供一种用于报告存储在数据处理器的存储装置中的数据中的错误的装置，包括：用于存储多个数字第一信号的第一装置; 用于存储所述多个数字第一信号并适于存储至少一个数字第二信号的第二装置; 用于将所述多个数字第一信号基本上从所述第一装置发送到所述第二装置的第三装置; 第四装置，用于在所述第三装置发送所述第一信号的过程中，响应于在所述多个数字第一信号中的一个或多个中出现一个或多个错误，提供所述至少一个数字第二信号; 用于将所述多个数字第一信号基本上从所述第二装置发送到所述第一装置的第五装置; 以及第六装置，适于在所述第五装置发送所述多个数字第一信号的过程中接收所述至少一个数字第二信号，并响应于所述至少一个数字第二信号的发生而提供至少一个第三信号。在每个数据流中，通过多个不同的检查块生成并应用ECC代码，以便最小化移入数据路径中的延迟，并且提供旁路数据路径，使得流可绕过所有错误检查和校正电路，并且主存储阵列与CPU之间的缓存设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式