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1. 发明授权

US5164893A Low inductance GTO switching circuit for an inverter 失效
标题翻译：用于逆变器的低电感GTO开关电路
公开(公告)号：US5164893A
公开(公告)日：1992-11-17
申请号：US734786
申请日：1991-07-23
申请人： Hansueli Luscher , Herbert Stemmler
发明人： Hansueli Luscher , Herbert Stemmler
IPC分类号： H02M1/06 , H02M7/515
CPC分类号： H02M7/515
摘要： With respect to their connection to snubber capacitors (C1, C2), a discharge resistor (12) connecting these snubber capacitors, and a link capacitor bank (3), inverter circuits with GTO thyristors (T1, T2) connected in series have parasitic leakage inductances which limit the level of the permissible link direct voltage. In order to reduce the leakage inductances, the snubber capacitors (C1, C2) are surrounded by effectively conducting capacitor covers (17). Sheet-metal shielding covers are fitted over the two ends of the discharge resistor (12). Parallel and series connected capacitors of the link capacitor bank (3) are connected to the positive/negative terminals (23, 24) of the GTO thyristors (T1, T2) in the middle of a heat sink connecting strainer (33), the supply leads being guided essentially parallel and the capacitors being arranged in opposite planes.
摘要翻译：关于缓冲电容器（C1，C2）的连接，连接这些缓冲电容器的放电电阻器（12）和连接电容器组（3），串联连接的具有GTO晶闸管（T1，T2）的反相器电路具有寄生泄漏限制可允许链路直流电压电平的电感。为了减小漏电感，缓冲电容器（C1，C2）被有效地传导电容器盖（17）包围。钣金屏蔽罩安装在放电电阻（12）的两端。连接电容器组（3）的并联和串联电容器连接到散热器连接过滤器（33）中间的GTO晶闸管（T1，T2）的正/负端子（23,24），供电引线基本上是平行的，并且电容器布置在相对的平面中。

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