专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5170375A Hierarchically constructed memory having static memory cells 失效
标题翻译：具有静态存储单元的分层构造的存储器
公开(公告)号：US5170375A
公开(公告)日：1992-12-08
申请号：US782798
申请日：1991-09-18
申请人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
发明人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
IPC分类号： G11C5/02 , G11C8/12 , G11C11/417 , G11C11/418 , G11C11/419
CPC分类号： G11C5/025 , G11C11/417 , G11C11/418 , G11C11/419 , G11C8/12
摘要： A static memory is constructed in a plurality of hierarchy levels. Beneficial realization possibilities are set forth with respect to the surface utilization for the drive and read-out circuits in the second hierarchy level which are especially critical. Memory cells that supply a strong cell signal are advantageously utilized so that a low expense is needed in the read circuit. By displacing periphery circuits into higher hierarchy levels, a short access time and a reduced surface requirement arise.
摘要翻译：静态存储器被构造在多个层级中。关于特别关键的第二层次的驱动和读出电路的表面利用率，阐述了有益的实现可能性。有利地利用提供强信元信号的存储单元，从而在读电路中需要低成本。通过将外围电路移位到更高级别的层次，出现短的访问时间和减小的表面要求。

2. 发明授权

US5040146A Static memory cell 失效
标题翻译：静态存储单元
公开(公告)号：US5040146A
公开(公告)日：1991-08-13
申请号：US491201
申请日：1990-03-09
申请人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
发明人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
IPC分类号： G11C8/16 , G11C11/412
CPC分类号： G11C8/16 , G11C11/412
摘要： Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.
摘要翻译：公开了存储器单元，当它们被用于静态存储器模块中时，避免在存储器外围电路中利用模拟电路，并且旨在在面临技术修改和参数波动时提高干扰的可靠性。通过写入选择晶体管从写入数据线发生写入，并且通过读取选择晶体管将读出发生到读取数据线上。由两个场效应晶体管形成的第二反相器用作反馈元件，以便静态地维持单元信息。由于在第一和第二逆变器之间的尺寸确定方面的不对称性，当与先前已知的存储器单元相比时，存储器单元在读出时显着地较不易于信息丢失。这些存储单元不需要读取数据线的预充电。

3. 发明授权

US5012450A Read amplifier for static memories in CMOS technology 失效
标题翻译：在CMOS技术中用于静态存储器的读取放大器
公开(公告)号：US5012450A
公开(公告)日：1991-04-30
申请号：US222006
申请日：1988-07-08
申请人： Hans-Juergen Mattausch , Klaus Althoff , Gerd Neuendorf
发明人： Hans-Juergen Mattausch , Klaus Althoff , Gerd Neuendorf
IPC分类号： G11C11/417 , G11C7/06 , G11C11/419
CPC分类号： G11C11/419 , G11C7/062
摘要： A read amplifier formed of a load component (L), a differential amplifier component (DIFF), a compensation transistor (N6), a switching transistor (P1) connected between a supply voltage (V.sub.DD) and the load component (L). The pre-loading potential of the read amplifier at its outputs LA, LA is about 2.5 volts. During the pre-loading phase, the two supply voltages (V.sub.DD, V.sub.22 =ground) are disconnected and the pre-loading potential is established by compensation of capacitances at the outputs LA, LA which results in an improved read amplifier.
摘要翻译：由负载分量（L），差分放大器分量（DIFF），补偿晶体管（N6），连接在电源电压（VDD）和负载分量（L）之间的开关晶体管（P1））构成的读取放大器。在其输出LA，LA处的读取放大器的预加载电位约为2.5伏特。在预加载阶段，两个电源电压（VDD，V22 =接地）断开，并且通过在输出LA，+ E，OVS / LA /上的电容补偿来建立预加载电位，这导致改进的读数放大器

4. 发明授权

US4893184A Arrangement for DPCM-coding with high data rate 失效
标题翻译：具有高数据速率的DPCM编码方案
公开(公告)号：US4893184A
公开(公告)日：1990-01-09
申请号：US346084
申请日：1989-05-01
申请人： Hans-Juergen Mattausch , Fred Matthiesen , Matthias Schoebinger
发明人： Hans-Juergen Mattausch , Fred Matthiesen , Matthias Schoebinger
IPC分类号： G06T9/00 , H03M3/04 , H03M7/36 , H04N19/50
CPC分类号： H04N19/50 , H03M7/3044
摘要： An arrangement for DPCM coding with high data rate. In a DPCM coder, wherein respective prediction values (s) are subtracted from digitized picture element signals (s), the difference signals that result represent the prediction error .DELTA. supplied to a circuit element for cutputting a quantization error (11) pertaining to a difference signal. In a following adder, quantization errors (q) are added to the prediction errors (.DELTA.), whereby the quantized prediction error (.DELTA.q) can be taken at the output of the following adder. For forming the reconstructed picture element signal (s.sub.R), the quantization error (q) is added to the current picture element signal (s) in a first adder and is supplied to a first subtraction means via a predictor. In an embodiment of the circuit, a DPCM structure that has a shortest possible critical path for a DPCM structure that is composed of a quantizer, of an addition and of a register can be produced by dividing the predictor upon insertion or removal of individual registers.
摘要翻译：具有高数据速率的DPCM编码的布置。在DPCM编码器中，其中从数字化的图像元素信号中减去各个预测值（+ E，cir / s /），结果的差分信号表示提供给用于计算量化误差的电路元件的预测误差DELTA 11）关于差分信号。在下面的加法器中，将量化误差（q）加到预测误差（DELTA）中，由此可以在随后的加法器的输出处获得量化预测误差（DELTA q）。为了形成重建的像素信号（sR），量化误差（q）被加到第一加法器中的当前像素信号中，并且经由预测器被提供给第一减法装置。在电路的一个实施例中，可以通过在插入或移除各个寄存器时分割预测器来产生具有由量化器，加法和寄存器组成的DPCM结构具有最短可能关键路径的DPCM结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式