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1. 发明授权

US07537883B2 Method of manufacturing nano size-gap electrode device 有权
标题翻译：制造纳米尺寸间隙电极器件的方法
公开(公告)号：US07537883B2
公开(公告)日：2009-05-26
申请号：US11447820
申请日：2006-06-06
申请人： Han Young Yu , In Bok Baek , Chang Geun Ahn , Ki Ju Im , Jong Heon Yang , Ung Hwan Pi , Min Ki Ryu , Chan Woo Park , Sung Yool Choi , Seong Jae Lee
发明人： Han Young Yu , In Bok Baek , Chang Geun Ahn , Ki Ju Im , Jong Heon Yang , Ung Hwan Pi , Min Ki Ryu , Chan Woo Park , Sung Yool Choi , Seong Jae Lee
IPC分类号： G03F7/00 , H01L51/40 , C25D5/18
CPC分类号： H01L51/105 , B82Y10/00 , H01L51/0023 , H01L51/0595
摘要： Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.
摘要翻译：提供一种制造纳米尺寸间隙电极器件的方法。该方法包括以下步骤：在半导体层上设置漂浮的纳米结构; 形成具有至少一个开口图案以与纳米结构相交的掩模层; 以及在通过所述开口图案暴露的所述半导体层上沉积金属以形成电极，使得通过所述纳米结构在所述纳米结构下方提供纳米尺寸间隙。

2. 发明申请

US20070072336A1 Method of manufacturing nano size-gap electrode device 有权
标题翻译：制造纳米尺寸间隙电极器件的方法
公开(公告)号：US20070072336A1
公开(公告)日：2007-03-29
申请号：US11447820
申请日：2006-06-06
申请人： Han Young Yu , In Bok Baek , Chang Geun Ahn , Ki Ju Im , Jong Heon Yang , Ung Hwan Pi , Min Ki Ryu , Chan Woo Park , Sung Yool Choi , Seong Jae Lee
发明人： Han Young Yu , In Bok Baek , Chang Geun Ahn , Ki Ju Im , Jong Heon Yang , Ung Hwan Pi , Min Ki Ryu , Chan Woo Park , Sung Yool Choi , Seong Jae Lee
IPC分类号： H01L51/40 , C25D5/18
CPC分类号： H01L51/105 , B82Y10/00 , H01L51/0023 , H01L51/0595
摘要： Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.
摘要翻译：提供一种制造纳米尺寸间隙电极器件的方法。该方法包括以下步骤：在半导体层上设置浮动的纳米结构; 形成具有至少一个开口图案以与纳米结构相交的掩模层; 以及在通过所述开口图案暴露的所述半导体层上沉积金属以形成电极，使得通过所述纳米结构在所述纳米结构下方提供纳米尺寸间隙。

3. 发明授权

US07947585B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07947585B2
公开(公告)日：2011-05-24
申请号：US12090891
申请日：2006-12-04
申请人： In Bok Baek , Seong Jae Lee , Jong Heon Yang , Chang Geun Ahn , Han Young Yu , Ki Ju Im
发明人： In Bok Baek , Seong Jae Lee , Jong Heon Yang , Chang Geun Ahn , Han Young Yu , Ki Ju Im
IPC分类号： H01L21/22
CPC分类号： H01L29/66439 , B82Y10/00 , H01L21/0273 , H01L21/28123 , H01L29/66484 , H01L29/66545 , H01L29/66575 , H01L29/66772 , H01L29/7613 , H01L29/7831
摘要： Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.
摘要翻译：提供了通过光刻处理改变光致抗蚀剂的特性以形成虚拟结构的半导体器件的制造方法，并且将该结构应用于形成栅电极的工艺。该方法包括以下步骤：在半导体衬底的顶部上形成缓冲层; 在缓冲层上施加无机光致抗蚀剂，并使用光刻工艺形成光致抗蚀剂图案; 使用预定气体热处理光刻胶图案; 在热处理结构上均匀沉积绝缘层，并通过沉积的厚度蚀刻沉积层，以暴露热处理的光致抗蚀剂图案; 在蚀刻的结构上沉积绝缘层，并蚀刻沉积的绝缘层以暴露热处理的光致抗蚀剂图案; 使用蚀刻工艺去除曝光的光致抗蚀剂图案; 在除去光致抗蚀剂图案的部分中形成栅氧化层; 以及在所述栅极氧化物层上形成栅电极。因此，在形成纳米尺寸器件的制造结构时，通过热处理提高了通过光刻工艺形成的层的性质，因此可以容易地形成用于制造各种器件的结构。

4. 发明申请

US20080254606A1 Method of Manufacturing Semiconductor Device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080254606A1
公开(公告)日：2008-10-16
申请号：US12090891
申请日：2006-12-04
申请人： In Bok Baek , Seong Jae Lee , Jong Heon Yang , Chang Geun Ahn , Han Young Yu , Ki Ju Im
发明人： In Bok Baek , Seong Jae Lee , Jong Heon Yang , Chang Geun Ahn , Han Young Yu , Ki Ju Im
IPC分类号： H01L21/28
CPC分类号： H01L29/66439 , B82Y10/00 , H01L21/0273 , H01L21/28123 , H01L29/66484 , H01L29/66545 , H01L29/66575 , H01L29/66772 , H01L29/7613 , H01L29/7831
摘要： Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.
摘要翻译：提供了通过光刻处理改变光致抗蚀剂的特性以形成虚拟结构的半导体器件的制造方法，并且将该结构应用于形成栅电极的工艺。该方法包括以下步骤：在半导体衬底的顶部上形成缓冲层; 在缓冲层上施加无机光致抗蚀剂，并使用光刻工艺形成光致抗蚀剂图案; 使用预定气体热处理光刻胶图案; 在热处理结构上均匀沉积绝缘层，并通过沉积的厚度蚀刻沉积层，以暴露热处理的光致抗蚀剂图案; 在蚀刻的结构上沉积绝缘层，并蚀刻沉积的绝缘层以暴露热处理的光致抗蚀剂图案; 使用蚀刻工艺去除曝光的光致抗蚀剂图案; 在除去光致抗蚀剂图案的部分中形成栅氧化层; 以及在所述栅极氧化物层上形成栅电极。因此，在形成纳米尺寸器件的制造结构时，通过热处理提高了通过光刻工艺形成的层的性质，因此可以容易地形成用于制造各种器件的结构。

5. 发明申请

US20110139637A1 METHOD AND APPARATUS FOR MEASURING ISOELECTRIC POINT USING FIELD EFFECT TRANSISTOR 失效
标题翻译：使用场效应晶体管测量电压点的方法和装置
公开(公告)号：US20110139637A1
公开(公告)日：2011-06-16
申请号：US13058120
申请日：2008-12-16
申请人： Chil Seong Ah , Ansoon Kim , Chan Woo Park , Chang-Geun Ahn , Jong-Heon Yang , In Bok Baek , Taeyoub Kim , Gun Yong Sung , Seon-Hee Park , Han Young Yu
发明人： Chil Seong Ah , Ansoon Kim , Chan Woo Park , Chang-Geun Ahn , Jong-Heon Yang , In Bok Baek , Taeyoub Kim , Gun Yong Sung , Seon-Hee Park , Han Young Yu
IPC分类号： G01N27/403 , G01N27/414
CPC分类号： G01N27/4145
摘要： Provided are a method and apparatus for measuring an isoelectric point using a field effect transistor. The method includes providing a field effect transistor including a substrate, source and drain electrodes disposed on the substrate and spaced apart from each other, and a channel region between the source and drain electrodes, providing a first electrolyte solution having a first concentration to the channel region of the field effect transistor and measuring a first current value of the channel region between the source and drain electrodes, providing a second electrolyte solution having a second concentration greater than the first concentration and measuring a second current value of the channel region between the source and drain electrodes, and determining as the isoelectric point of the field effect transistor or a material disposed on the field effect transistor using a difference between the first and second current values.
摘要翻译：提供了使用场效应晶体管测量等电点的方法和装置。该方法包括提供场效应晶体管，该场效应晶体管包括衬底，设置在衬底上的源电极和漏极彼此间隔开的沟道区，以及在源电极和漏电极之间的沟道区域，提供具有第一浓度到沟道的第一电解质溶液区域，并且测量源极和漏极之间的沟道区的第一电流值，提供具有大于第一浓度的第二浓度的第二电解质溶液，并测量源极之间的沟道区的第二电流值和漏电极，并且使用第一和第二电流值之间的差来确定场效应晶体管的等电点或设置在场效应晶体管上的材料。

6. 发明授权

US07893466B2 Semiconductor FET sensor and method of fabricating the same 有权
标题翻译：半导体FET传感器及其制造方法
公开(公告)号：US07893466B2
公开(公告)日：2011-02-22
申请号：US12195302
申请日：2008-08-20
申请人： Jong Heon Yang , In Bok Baek , Chang Geun Ahn , Chan Woo Park , An Soon Kim , Han Young Yu , Chil Seong Ah , Tae Youb Kim , Myung Sim Jun , Moon Gyu Jang
发明人： Jong Heon Yang , In Bok Baek , Chang Geun Ahn , Chan Woo Park , An Soon Kim , Han Young Yu , Chil Seong Ah , Tae Youb Kim , Myung Sim Jun , Moon Gyu Jang
IPC分类号： G01N27/403
CPC分类号： G01N27/4145 , H01L29/66818 , H01L29/7853
摘要： Provided are a semiconductor Field-Effect Transistor (FET) sensor and a method of fabricating the same. The method includes providing a semiconductor substrate, forming a sensor structure having a fin-shaped structure on the semiconductor substrate, injecting ions for electrical ohmic contact into the sensor structure, and depositing a metal electrode on the sensor structure, immobilizing a sensing material to be specifically combined with a target material onto both sidewall surfaces of the fin-shaped structure, and forming a passage on the sensor structure such that the target material passes through the fin-shaped structure.
摘要翻译：提供了一种半导体场效应晶体管（FET）传感器及其制造方法。该方法包括提供半导体衬底，在半导体衬底上形成具有鳍状结构的传感器结构，将用于电欧姆接触的离子注入到传感器结构中，以及在传感器结构上沉积金属电极，将感测材料固定为特别地将目标材料组合到鳍状结构的两个侧壁表面上，并且在传感器结构上形成通道，使得目标材料通过鳍状结构。

7. 发明授权

US08628650B2 Method and apparatus for measuring isoelectric point using field effect transistor 失效
标题翻译：使用场效应晶体管测量等电点的方法和装置
公开(公告)号：US08628650B2
公开(公告)日：2014-01-14
申请号：US13058120
申请日：2008-12-16
申请人： Chil Seong Ah , Ansoon Kim , Chan Woo Park , Chang-Geun Ahn , Jong-Heon Yang , In Bok Baek , Taeyoub Kim , Gun Yong Sung , Seon-Hee Park , Han Young Yu
发明人： Chil Seong Ah , Ansoon Kim , Chan Woo Park , Chang-Geun Ahn , Jong-Heon Yang , In Bok Baek , Taeyoub Kim , Gun Yong Sung , Seon-Hee Park , Han Young Yu
IPC分类号： B03C5/02
CPC分类号： G01N27/4145
摘要： Provided are a method and apparatus for measuring an isoelectric point using a field effect transistor. The method includes providing a field effect transistor including a substrate, source and drain electrodes disposed on the substrate and spaced apart from each other, and a channel region between the source and drain electrodes, providing a first electrolyte solution having a first concentration to the channel region of the field effect transistor and measuring a first current value of the channel region between the source and drain electrodes, providing a second electrolyte solution having a second concentration greater than the first concentration and measuring a second current value of the channel region between the source and drain electrodes, and determining the isoelectric point of the field effect transistor or a material disposed on the field effect transistor using a difference between the first and second current values.
摘要翻译：提供了使用场效应晶体管测量等电点的方法和装置。该方法包括提供场效应晶体管，该场效应晶体管包括衬底，设置在衬底上的源电极和漏极彼此间隔开的沟道区，以及在源电极和漏电极之间的沟道区域，提供具有第一浓度到沟道的第一电解质溶液区域，并且测量源极和漏极之间的沟道区的第一电流值，提供具有大于第一浓度的第二浓度的第二电解质溶液，并测量源极之间的沟道区的第二电流值和漏电极，并且使用第一和第二电流值之间的差来确定场效应晶体管的等电点或设置在场效应晶体管上的材料。

8. 发明授权

US08241939B2 Semiconductor nanowire sensor device and method for manufacturing the same 有权
标题翻译：半导体纳米线传感器装置及其制造方法
公开(公告)号：US08241939B2
公开(公告)日：2012-08-14
申请号：US12682571
申请日：2008-07-24
申请人： Chan Woo Park , Chang Geun Ahn , Jong Heon Yang , In Bok Baek , Chil Seong Ah , Han Young Yu , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Myung Sim Jun
发明人： Chan Woo Park , Chang Geun Ahn , Jong Heon Yang , In Bok Baek , Chil Seong Ah , Han Young Yu , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Myung Sim Jun
IPC分类号： H01L21/00 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y15/00 , H01L29/0673 , H01L29/78696
摘要： A method for manufacturing a biosensor includes forming a silicon nanowire channel, etching a first conductivity-type single crystalline silicon layer which is a top layer of a Silicon-On-Insulator (SOI) substrate to form a first conductivity-type single crystalline silicon line pattern, doping both sidewalls of the first conductivity-type single crystalline silicon line pattern with impurities of a second conductivity-type opposite to the first conductivity-type to form a second conductivity-type channel, forming second conductivity-type pads for forming electrodes at both ends of the first conductivity-type single crystalline silicon line pattern, forming, in an undoped region of the first conductivity-type single crystalline silicon line pattern, a first electrode for applying a reverse-bias voltage to insulate the first conductivity-type single crystalline silicon line pattern and the second conductivity-type channel from each other, and forming second electrodes for applying a bias voltage across the second conductivity-type channel on the second conductivity-type pad.
摘要翻译：制造生物传感器的方法包括形成硅纳米线通道，蚀刻作为绝缘体上硅（SOI）衬底的顶层的第一导电型单晶硅层，以形成第一导电型单晶硅线以与第一导电类型相反的第二导电类型的杂质掺杂第一导电型单晶硅线图案的两个侧壁以形成第二导电型沟道，形成第二导电型垫，用于在第一导电型单晶硅线图案的两端，在第一导电型单晶硅线图案的未掺杂区域中形成用于施加反向偏置电压以使第一导电型单晶硅线型图案绝缘的第一电极晶体硅线图案和第二导电型沟道，并且形成用于施加双面的第二电极在第二导电型垫上的第二导电类型沟道上的电压。

9. 发明申请

US20110194976A1 DETECTION DEVICE AND SYSTEM 有权
标题翻译：检测装置和系统
公开(公告)号：US20110194976A1
公开(公告)日：2011-08-11
申请号：US12682545
申请日：2008-06-13
申请人： Chang Geun Ahn , Chan Woo Park , Jong Heon Yang , In Bok Baek , Chil Seong Ah , Han Young Yu , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Seon Hee Park
发明人： Chang Geun Ahn , Chan Woo Park , Jong Heon Yang , In Bok Baek , Chil Seong Ah , Han Young Yu , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Seon Hee Park
IPC分类号： G01N33/48 , H01L27/06
CPC分类号： G01N27/4145 , Y10T436/11
摘要： A detection device and system are provided. The detection device includes a detection capacitor and a Field Effect Transistor (FET). The detection capacitor has a reactive material layer reacting to a specific functional group in a fluid, and first and second electrodes disposed on the both surfaces of an insulating layer, and the FET has a source electrode connected with the second electrode, a gate electrode connected with the first electrode, and a drain electrode. Here, the insulating layer of the detection capacitor is thicker than a gate insulating layer of the FET.
摘要翻译：提供检测装置和系统。检测装置包括检测电容器和场效应晶体管（FET）。检测电容器具有与流体中的特定官能团反应的反应性物质层，以及设置在绝缘层两面的第一和第二电极，并且所述FET具有与所述第二电极连接的源电极，连接有栅电极与第一电极和漏电极。这里，检测电容器的绝缘层比FET的栅极绝缘层厚。

10. 发明授权

US08263964B2 Three-dimensional nanodevices including nanostructures 有权
标题翻译：包括纳米结构在内的三维纳米器件
公开(公告)号：US08263964B2
公开(公告)日：2012-09-11
申请号：US12672995
申请日：2008-05-19
申请人： Han Young Yu , Byung Hoon Kim , An Soon Kim , In Bok Baek , Chil Seong Ah , Jong Heon Yang , Chan Woo Park , Chang Geun Ahn
发明人： Han Young Yu , Byung Hoon Kim , An Soon Kim , In Bok Baek , Chil Seong Ah , Jong Heon Yang , Chan Woo Park , Chang Geun Ahn
IPC分类号： H01L29/06
CPC分类号： H01J49/4205 , B81B7/0025 , B81B2201/0214 , B81B2201/0271 , B82Y10/00 , B82Y40/00 , G01N2291/0257 , H01J49/0018 , H01L29/0673 , H01L29/7613 , H01L29/775 , H03H2009/02314
摘要： Provided are three-dimensional (3D) nanodevices including 3D nanostructures. The 3D nanodevice includes at least one nanostructure, each nanostructure including an oscillation portion floating over a substrate and support portions for supporting both lengthwise end portions of the oscillation portion, supports disposed on the substrate to support the support portions of each of the nanostructures, at least one controller disposed at an upper portion of the substrate, a lower portion of the substrate, or both the upper and lower portions of the substrate to control each of the nanostructures, and a sensing unit disposed on each of the oscillation portions to sense an externally supplied adsorption material. Thus, unlike in a typical planar device, generation of impurities between a nanodevice and a substrate can be reduced, and mechanical vibration can be caused. In particular, since 3D nanostructures have mechanical and electrical characteristics, 3D nanodevices including new 3D nanostructures can be provided using nano-electro-mechanical systems (NEMS). Also, a single electron device, a spin device, or a single electron transistor (SET)-field effect transistor (FET) hybrid device can be formed using a simple process unlike in planar devices.
摘要翻译：提供了三维（3D）纳米器件，包括3D纳米结构。 3D纳米装置包括至少一个纳米结构，每个纳米结构包括漂浮在基板上的振荡部分和支撑部分，用于支撑振荡部分的两个纵向端部，支撑件设置在基板上以支撑每个纳米结构的支撑部分，设置在基板的上部，基板的下部或基板的上部和下部的至少一个控制器，以控制每个纳米结构;以及感测单元，设置在每个振荡部分上以感测外部供应的吸附材料。因此，与典型的平面器件不同，可以减少纳米器件与衬底之间的杂质的产生，并且可能引起机械振动。特别地，由于3D纳米结构具有机械和电学特性，可以使用纳米机电系统（NEMS）提供包括新的3D纳米结构的3D纳米器件。此外，可以使用与平面器件不同的简单工艺来形成单电子器件，自旋器件或单电子晶体管（SET）场效应晶体管（FET）混合器件。

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