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1. 发明授权

US06521538B2 Method of forming a trench with a rounded bottom in a semiconductor device 有权
标题翻译：在半导体器件中形成具有圆形底部的沟槽的方法
公开(公告)号：US06521538B2
公开(公告)日：2003-02-18
申请号：US09790888
申请日：2001-02-23
申请人： Hajime Soga , Kenji Kondo , Eiji Ishikawa , Yoshikazu Sakano , Mikimasa Suzuki
发明人： Hajime Soga , Kenji Kondo , Eiji Ishikawa , Yoshikazu Sakano , Mikimasa Suzuki
IPC分类号： H01L21311
CPC分类号： H01L29/7813 , H01L21/76232 , H01L21/763 , H01L29/4236 , H01L29/66348
摘要： In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, isotropic etching is performed to round a corner of a bottom portion of the trench without removing the reaction product. The isotropic etching can round the corner of the trench without etching the side wall of the trench that is covered by the reaction product.
摘要翻译：在制造半导体器件的方法中，首先，通过各向异性蚀刻在半导体衬底上形成沟槽，并且在各向异性蚀刻期间，在沟槽的内壁上产生并沉积反应产物。然后，进行各向同性蚀刻，以在沟槽的底部的一个角部周围，而不去除反应产物。各向同性蚀刻可以围绕沟槽的角落，而不蚀刻由反应产物覆盖的沟槽的侧壁。

2. 发明授权

US06469345B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06469345B2
公开(公告)日：2002-10-22
申请号：US09758377
申请日：2001-01-12
申请人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga
发明人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L21/28202 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film is composed of a first portion disposed on a side wall portion of the trench and a second portion disposed on upper and bottom portions of the trench. The first portion is composed of a first oxide film, a nitride film, and a second oxide film. The second portion is composed of only an oxide film and has a thickness thicker than that of the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be mitigated, and a decrease in withstand voltage at that portions can be prevented.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜由设置在沟槽的侧壁部分上的第一部分和设置在沟槽的上部和底部的第二部分组成。第一部分由第一氧化物膜，氮化物膜和第二氧化物膜组成。第二部分仅由氧化膜构成，其厚度比第一部分厚。因此，可以减轻沟槽上下角部的电场集中，能够防止该部分的耐电压降低。

3. 发明授权

US07354829B2 Trench-gate transistor with ono gate dielectric and fabrication process therefor 有权
标题翻译：具有栅极电介质的沟槽栅晶体管及其制造工艺
公开(公告)号：US07354829B2
公开(公告)日：2008-04-08
申请号：US10974838
申请日：2004-10-28
申请人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga
发明人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。第二部分仅包括氧化膜并且比第一部分厚。因此，可以减小沟槽的上下角部的电场集中以提高耐压。此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

4. 发明申请

US20050090060A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050090060A1
公开(公告)日：2005-04-28
申请号：US10974838
申请日：2004-10-28
申请人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga , Takafumi Arakawa , Yukio Tsuzuki
发明人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga , Takafumi Arakawa , Yukio Tsuzuki
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。第二部分仅包括氧化膜并且比第一部分厚。因此，可以减小沟槽的上下角部的电场集中以提高耐压。此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

5. 发明申请

US20050133859A1 Semiconductor device and design-aiding program 失效
标题翻译：半导体器件和设计辅助程序
公开(公告)号：US20050133859A1
公开(公告)日：2005-06-23
申请号：US11012116
申请日：2004-12-16
申请人： Makoto Kuwahara , Yoshiyuki Hattori , Shoichi Yamauchi , Mikimasa Suzuki
发明人： Makoto Kuwahara , Yoshiyuki Hattori , Shoichi Yamauchi , Mikimasa Suzuki
IPC分类号： G06F17/50 , H01L27/02 , H01L29/06 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7813 , G06F17/5068 , H01L29/0634
摘要： A semiconductor device is fabricated to include a withstand-voltage assurance layer designed into a multi-dimensional super junction structure and a group of trench gate electrodes, each of which penetrating a body layer in contact with the multi-dimensional super junction structure to reach the multi-dimensional super junction structure, so that dispersions of an on-resistance of the semiconductor device can be reduced. When a position at which the group of trench gate electrodes is created is shifted in one direction, the size of an overlap area common to the group of trench gate electrodes and an n-type column changes. However, the group of trench gate electrodes is oriented in such a way that the changes in overlap-area size are minimized.
摘要翻译：半导体器件被制造成包括设计成多维超结结构的耐压保证层和一组沟槽栅极电极，每个沟槽栅电极穿透与多维超结结构接触的体层以达到多维超结结构，能够降低半导体装置的导通电阻的分散。当形成沟槽栅电极组的位置在一个方向上移动时，沟槽栅电极组和n型列共同的重叠区域的尺寸改变。然而，沟槽栅电极组被定向成使得重叠区域尺寸的变化最小化。

6. 发明授权

US06864532B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06864532B2
公开(公告)日：2005-03-08
申请号：US10175294
申请日：2002-06-20
申请人： Takaaki Aoki , Akira Kuroyanagi , Mikimasa Suzuki , Takafumi Arakawa , Yukio Tsuzuki
发明人： Takaaki Aoki , Akira Kuroyanagi , Mikimasa Suzuki , Takafumi Arakawa , Yukio Tsuzuki
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。第二部分仅包括氧化膜并且比第一部分厚。因此，可以减小沟槽的上下角部的电场集中以提高耐压。此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

7. 发明授权

US07364971B2 Method for manufacturing semiconductor device having super junction construction 有权
标题翻译：具有超结构构造的半导体器件的制造方法
公开(公告)号：US07364971B2
公开(公告)日：2008-04-29
申请号：US11356984
申请日：2006-02-21
申请人： Hitoshi Yamaguchi , Mikimasa Suzuki , Yoshiyuki Hattori
发明人： Hitoshi Yamaguchi , Mikimasa Suzuki , Yoshiyuki Hattori
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1095
摘要： A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.
摘要翻译：半导体器件包括主体区域，具有第一部分和第二部分的漂移区域以及沟槽栅电极。身体区域设置在漂移区域上。第一和第二部分沿延伸方向延伸，使得第二部分与第一部分相邻。沟槽栅电极穿透体区并到达漂移区，使得沟槽栅电极通过绝缘层面向体区和漂移区。沟槽栅电极沿与第一和第二部分的延伸方向交叉的方向延伸。第一部分包括沟槽栅电极附近的部分，其杂质浓度等于或低于体区的杂质浓度。

8. 发明授权

US07307312B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07307312B2
公开(公告)日：2007-12-11
申请号：US10817904
申请日：2004-04-06
申请人： Mikimasa Suzuki , Yoshiyuki Hattori , Kyoko Nakashima
发明人： Mikimasa Suzuki , Yoshiyuki Hattori , Kyoko Nakashima
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L29/7811 , H01L21/78 , H01L29/0634 , H01L29/0878 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device manufacturing method comprises forming a pn column so that the pn column is designed to have a strip form in the section of the substrate and have a repetitive pattern of a p-conduction type and an n-conduction type on the substrate surface over an area where plural semiconductor devices having the same structure are formed in a semiconductor substrate, forming residual constituent elements of the plural semiconductor devices having the same structure in areas where the repetitive patterns are located while the pn column serves as a part of the constituent element of each semiconductor device, and dicing the individual semiconductor devices into chips from the area where the plural semiconductor devices having the same structure are formed.
摘要翻译：半导体器件制造方法包括形成pn列，使得pn列被设计为在衬底的部分中具有条形，并且在衬底表面上具有p导电型和n导电型的重复图案，在半导体衬底中形成具有相同结构的多个半导体器件的区域，在pn列用作构成元件的一部分的同时，在重复图案所在的区域中形成具有相同结构的多个半导体器件的残留构成元件并且从形成有相同结构的多个半导体器件的区域将各个半导体器件切割成芯片。

9. 发明授权

US07345339B2 Vertical channel FET with super junction construction 有权
标题翻译：具有超结结构的垂直沟道FET
公开(公告)号：US07345339B2
公开(公告)日：2008-03-18
申请号：US10872789
申请日：2004-06-22
申请人： Hitoshi Yamaguchi , Mikimasa Suzuki , Yoshiyuki Hattori
发明人： Hitoshi Yamaguchi , Mikimasa Suzuki , Yoshiyuki Hattori
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1095
摘要： A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.
摘要翻译：半导体器件包括主体区域，具有第一部分和第二部分的漂移区域以及沟槽栅电极。身体区域设置在漂移区域上。第一和第二部分沿延伸方向延伸，使得第二部分与第一部分相邻。沟槽栅电极穿透体区并到达漂移区，使得沟槽栅电极通过绝缘层面向体区和漂移区。沟槽栅电极沿与第一和第二部分的延伸方向交叉的方向延伸。第一部分包括沟槽栅电极附近的部分，其杂质浓度等于或低于体区的杂质浓度。

10. 发明授权

US07148125B2 Method for manufacturing semiconductor power device 有权
公开(公告)号：US07148125B2
公开(公告)日：2006-12-12
申请号：US10310021
申请日：2002-12-05
申请人： Mikimasa Suzuki , Chikage Noritake
发明人： Mikimasa Suzuki , Chikage Noritake
IPC分类号： H01L21/46 , H01L21/302
CPC分类号： H01L29/7813 , H01L21/02035 , H01L29/0657 , H01L29/0661 , H01L29/66348
摘要： A semiconductor device, which has a relatively low ON resistance, is manufactured using the following steps. First, a semiconductor wafer that includes a semiconductor layer and a semiconductor element layer, which is located on the semiconductor layer, is formed. Then, the wafer is ground evenly to a predetermined thickness from the side where the semiconductor layer is located. Next, the wafer is etched to a predetermined thickness from the side where the semiconductor layer is located while the periphery of the wafer is masked against the etchant to form a rim at the periphery. The wafer is reinforced by the rim at the periphery, so even if the wafer is relatively large, the wafer is prevented from breaking or warping at the later steps after the wafer is thinned by etching.

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