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    • 1. 发明申请
    • Data processing device and data recording method
    • 数据处理装置和数据记录方法
    • US20060280480A1
    • 2006-12-14
    • US11504151
    • 2006-08-15
    • Hajime NittaToshimichi HamadaMasashi OhtaKiyoshi Ota
    • Hajime NittaToshimichi HamadaMasashi OhtaKiyoshi Ota
    • H04N7/00
    • H04N9/8042H04N5/781H04N5/783H04N9/7921H04N9/8063
    • A data processing device includes a video input/output circuit for inputting an input video signal and outputting an output video signal. A detection circuit detects a first synchronizing signal in the input video signal input. Using a second synchronizing signal different from the first synchronizing signal, the video input/output circuit outputs the output video signal. The data processing device further includes a storage medium, a controller and an audio input circuit for inputting an audio signal using the second synchronizing signal. The controller controls recording of the inputted audio signal through the audio input circuit and recording of the output video signal onto the storage medium, such that the inputted audio signal and the output video signal are synchronized by the second synchronizing signal.
    • 数据处理装置包括用于输入输入视频信号并输出​​输出视频信号的视频输入/输出电路。 检测电路检测输入视频信号输入中的第一同步信号。 使用与第一同步信号不同的第二同步信号,视频输入/输出电路输出输出视频信号。 数据处理装置还包括存储介质,控制器和用于使用第二同步信号输入音频信号的音频输入电路。 控制器控制通过音频输入电路输入的音频信号的记录,并将输出视频信号记录到存储介质上,使得输入的音频信号和输出视频信号由第二同步信号同步。
    • 4. 发明授权
    • Data recording/reproducing device
    • 数据记录/再现装置
    • US06757484B2
    • 2004-06-29
    • US09812167
    • 2001-03-19
    • Hajime NittaToshimichi HamadaMasashi OhtaKiyoshi Ota
    • Hajime NittaToshimichi HamadaMasashi OhtaKiyoshi Ota
    • H04N591
    • H04N9/8042H04N5/781H04N9/7921H04N9/8063
    • A system for recording an input video signal input to an A/D conversion processing section on a recording medium in accordance with a recording clock generated by a recording system synchronous control section, and for outputting the video signal recorded on the recording medium to outside in accordance with a reproducing system synchronous control section. When switching and outputting a recording video signal input to the A/D conversion processing section and a reproduction video signal recorded on the recording medium and then decoded and output by an MPEG AV decoder, the recording video signal is temporarily stored in a frame synchronizer, and the recording video signal stored in the frame synchronizer and the reproduction video signal decoded by the MPEG AV decoder are switched and output in accordance with a reproduction clock generated by the reproducing system synchronous control section.
    • 一种用于根据由记录系统同步控制部产生的记录时钟将输入到A / D转换处理部分的输入视频信号记录在记录介质上并将记录在记录介质上的视频信号输出到外部的系统 符合再现系统同步控制部分。 当切换和输出输入到A / D转换处理部分的记录视频信号和记录在记录介质上的再现视频信号,然后由MPEG AV解码器解码和输出时,记录视频信号被临时存储在帧同步器中, 并且存储在帧同步器中的记录视频信号和由MPEG AV解码器解码的再现视频信号根据由再现系统同步控制部分生成的再现时钟被切换和输出。
    • 6. 发明授权
    • Data multiplexer, data multiplexing method, and recording medium
    • 数据复用器,数据复用方法和记录介质
    • US07496675B2
    • 2009-02-24
    • US09824367
    • 2001-04-02
    • Koji ObataNoriaki OishiTomoyuki SatoHajime NittaKiyoshi Ota
    • Koji ObataNoriaki OishiTomoyuki SatoHajime NittaKiyoshi Ota
    • G06F15/16H06J3/24H06N7/12
    • H04N21/23406G11B20/10527H04N7/52H04N21/44004
    • FIG. 3B shows buffer occupancy rate of a transport stream buffer 21 when a TS packet is transferred to the transport stream buffer 21 having a transport rate Rt and a leak rate Rx. A time T1 during which the buffer occupancy rate of the transport stream buffer 21 increases and a time T2 during which the buffer occupancy rate of the transport stream buffer 21 decreases are expressed by (Rt−Rx)×T1=Rx×T2 and T1=(188×8)/Rt. A time T is T=T1+T2=(188×8)/Rx. Therefore, the time T is equal to a time T′ shown in FIG. 3C. Thus, when a TS packet is transferred in a cycle of the time T′, the transport stream buffer 21 will not overflow and the transport stream buffer 21 becomes empty at least once a second, whereby simulation for the transport stream buffer 21 is not required in the simulation for the T-STD model.
    • 图。 图3B示出了当TS分组被传送到具有传输速率Rt和泄漏速率Rx的传输流缓冲器21时的传输流缓冲器21的缓冲器占用率。 传输流缓冲器21的缓冲器占用率增加的时间T1和传输流缓冲器21的缓冲器占用率减小的时间T2由(Rt-Rx)xT1 = RxxT2和T1 =(188×8)表示, / Rt。 时间T为T = T1 + T2 =(188x8)/ Rx。 因此,时间T等于图1所示的时间T'。 3C。 因此,当在时间T'的周期中传送TS分组时,传输流缓冲器21将不会溢出,并且传输流缓冲器21至少一秒钟变空,由此不需要传输流缓冲器21的模拟 在T-STD模型的模拟中。