专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060277398A1 Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline 审中-公开
标题翻译：用于在无序流水线中执行指令等待时间的方法和装置
公开(公告)号：US20060277398A1
公开(公告)日：2006-12-07
申请号：US11145409
申请日：2005-06-03
申请人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan , Christopher Wilkerson
发明人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan , Christopher Wilkerson
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3814 , G06F9/383 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method and apparatus for setting aside a long-latency micro-operation from a reorder buffer is disclosed. In one embodiment, a long-latency micro-operation would conventionally stall a reorder buffer. Therefore a secondary buffer may be used to temporarily store that long-latency micro-operation, and other micro-operations depending from it, until that long-latency micro-operation is ready to execute. These micro-operations may then be reintroduced into the reorder buffer for execution. The use of poisoned bits may be used to ensure correct retirement of register values merged from both pre- and post-execution of the micro-operations which were set aside in the secondary buffer.
摘要翻译：公开了一种用于从重排序缓冲器中排除长延迟微操作的方法和装置。在一个实施例中，长时间延迟微操作通常会阻止重新排序缓冲器。因此，可以使用辅助缓冲器来临时存储长延迟微操作以及依赖于其的微操作，直到长时间延迟微操作准备好执行。然后可以将这些微操作重新引入重排序缓冲器中以供执行。可以使用中毒的位来确保正确地退出从辅助缓冲器中放置的微操作执行之前和之后合并的寄存器值。

2. 发明申请

US20050120191A1 Checkpoint-based register reclamation 审中-公开
标题翻译：基于检查点的寄存器回收
公开(公告)号：US20050120191A1
公开(公告)日：2005-06-02
申请号：US10724874
申请日：2003-12-02
申请人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： A processor enabled with checkpoints may be used to recover registers using counter entry and release.
摘要翻译：启用检查点的处理器可用于使用计数器条目和释放来恢复寄存器。

3. 发明申请

US20050120179A1 Single-version data cache with multiple checkpoint support 审中-公开
标题翻译：具有多个检查点支持的单版本数据缓存
公开(公告)号：US20050120179A1
公开(公告)日：2005-06-02
申请号：US10724863
申请日：2003-12-02
申请人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0875
摘要： A single-version data cache processes speculative stores using one or more checkpoints.
摘要翻译：单一版本的数据缓存使用一个或多个检查点处理投机存储。

4. 发明申请

US20050120192A1 Scalable rename map table recovery 失效
标题翻译：可扩展重命名映射表恢复
公开(公告)号：US20050120192A1
公开(公告)日：2005-06-02
申请号：US10724876
申请日：2003-12-02
申请人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan
IPC分类号： G06F9/00 , G06F9/38
CPC分类号： G06F9/3863 , G06F9/384 , G06F9/3842 , G06F9/3844
摘要： Checkpoints may be used to recover from branch mispredictions using scalable rename map table recovery.
摘要翻译：检查点可用于使用可伸缩重命名映射表恢复从分支错误预测中恢复。

5. 发明授权

US08190859B2 Critical section detection and prediction mechanism for hardware lock elision 有权
标题翻译：硬件锁定检测的关键部分检测和预测机制
公开(公告)号：US08190859B2
公开(公告)日：2012-05-29
申请号：US11599009
申请日：2006-11-13
申请人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
IPC分类号： G06F12/00
CPC分类号： G06F9/3865 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F9/528
摘要： A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.
摘要翻译：这里描述了用于检测锁定指令和锁定释放指令以及预测关键部分的方法和装置。检测逻辑检测到锁定指令，这可能存在于解码逻辑中。存储/创建与锁定指令相关联的锁定指令条目。将要写入后续潜在锁定释放指令的地址位置的地址位置和值与通过锁定指令加载的地址和锁定指令的值负载进行比较。如果地址和值匹配，则确定锁定释放指令与锁定指令匹配。预测条目存储对诸如最后指令指针（LIP）的锁定指令的引用，并且如果确定锁定解除指令与锁定相匹配，则在后续检测时将要消除表示锁定指令的关联值指令。

6. 发明授权

US07809903B2 Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions 有权
标题翻译：协调访问硬件事务内存事务和软件事务内存事务的内存位置
公开(公告)号：US07809903B2
公开(公告)日：2010-10-05
申请号：US11303529
申请日：2005-12-15
申请人： Ali-Reza Adl-tabatabai , Bratin Saha , Richard L. Hudson , Haitham Akkary , Ravi Rajwar
发明人： Ali-Reza Adl-tabatabai , Bratin Saha , Richard L. Hudson , Haitham Akkary , Ravi Rajwar
IPC分类号： G06F12/12
CPC分类号： G06F9/467 , G06F12/0815 , G06F2212/507
摘要： Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
摘要翻译：提供了一种用于协调对硬件事务存储器事务和软件事务存储器事务的存储器位置的访问的方法，系统和程序。在硬件事务存储器中执行的硬件事务发起访问存储器位置的请求。响应于在软件事务存储器中执行的一个软件事务的操作，故障返回到硬件事务请求。

7. 发明申请

US20070239942A1 Transactional memory virtualization 有权
标题翻译：事务性内存虚拟化
公开(公告)号：US20070239942A1
公开(公告)日：2007-10-11
申请号：US11394622
申请日：2006-03-30
申请人： Ravi Rajwar , Haitham Akkary , Konrad Lai
发明人： Ravi Rajwar , Haitham Akkary , Konrad Lai
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/467
摘要： Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.
摘要翻译：描述了以虚拟化模式提供事务性存储器执行的方法和装置。在一个实施例中，对应于事务存储器访问请求的数据可以在与事务存储器访问请求相对应的操作引起溢出并且可以针对溢出的发生更新存储的值之后存储在存储器的一部分中。

8. 发明申请

US20070143287A1 Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions 有权
标题翻译：协调访问硬件事务内存事务和软件事务内存事务的内存位置
公开(公告)号：US20070143287A1
公开(公告)日：2007-06-21
申请号：US11303529
申请日：2005-12-15
申请人： Ali-Reza Adl-tabatabai , Bratin Saha , Richard Hudson , Haitham Akkary , Ravi Rajwar
发明人： Ali-Reza Adl-tabatabai , Bratin Saha , Richard Hudson , Haitham Akkary , Ravi Rajwar
IPC分类号： G06F17/30
CPC分类号： G06F9/467 , G06F12/0815 , G06F2212/507
摘要： Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
摘要翻译：提供了一种用于协调对硬件事务存储器事务和软件事务存储器事务的存储器位置的访问的方法，系统和程序。在硬件事务存储器中执行的硬件事务发起访问存储器位置的请求。响应于在软件事务存储器中执行的一个软件事务的操作，故障返回到硬件事务请求。

9. 发明授权

US09798590B2 Post-retire scheme for tracking tentative accesses during transactional execution 有权
公开(公告)号：US09798590B2
公开(公告)日：2017-10-24
申请号：US11517029
申请日：2006-09-07
申请人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
IPC分类号： G06F9/44 , G06F9/52 , G06F9/38 , G06F9/30
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859
摘要： A method and apparatus for post-retire transaction access tracking is herein described. Load and store buffers are capable of storing senior entries. In the load buffer a first access is scheduled based on a load buffer entry. Tracking information associated with the load is stored in a filter field in the load buffer entry. Upon retirement, the load buffer entry is marked as a senior load entry. A scheduler schedules a post-retire access to update transaction tracking information, if the filter field does not represent that the tracking information has already been updated during a pendency of the transaction. Before evicting a line in a cache, the load buffer is snooped to ensure no load accessed the line to be evicted.

10. 发明申请

US20090119459A1 LATE LOCK ACQUIRE MECHANISM FOR HARDWARE LOCK ELISION (HLE) 有权
标题翻译：锁定锁定机构（HLE）
公开(公告)号：US20090119459A1
公开(公告)日：2009-05-07
申请号：US11936249
申请日：2007-11-07
申请人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F12/0815
摘要： A method and apparatus for a late lock acquire mechanism is herein described. In response to detecting a late-lock acquire event, such as expiration of a timer, a full cachet set, and an irrevocable event, a late-lock acquire may be initiated. Consecutive critical sections are stalled until a late-lock acquire is completed utilizing fields of access buffer entries associated with consecutive critical section operations.
摘要翻译：这里描述了一种用于后期锁定获取机制的方法和装置。响应于检测到延迟获取事件，例如定时器的到期，完整的记录集和不可撤销的事件，可以启动延迟锁定获取。连续的关键部分被停止，直到使用与连续关键部分操作相关联的访问缓冲器条目的字段来完成延迟锁定获取。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式