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    • 3. 发明申请
    • DRIVING CIRCUIT FOR LCD BACKLIGHT SOURCE
    • 液晶背光源驱动电路
    • US20120249008A1
    • 2012-10-04
    • US13433741
    • 2012-03-29
    • Liang ZHANGDan WANGWeihai LIShuai HOUXingji WU
    • Liang ZHANGDan WANGWeihai LIShuai HOUXingji WU
    • H05B37/02
    • H05B33/0815
    • A driving circuit for a LCD backlight source comprising a BOOST structure which comprises a capacitor C12, a capacitor C13, an inductor L2, a diode D2, and a MOSFET, wherein the driving circuit further comprises a capacitor C11, a capacitor C14, a diode D3, and a diode D4. One terminal of the diode D3 is connected to one terminal of the capacitor C13, and the other terminal is connected to one terminal of the diode D4; the other terminal of the diode D4 is connected to one terminal of the capacitor C14 which is the output terminal of the circuit, and the other terminal of the capacitor C14 is grounded; one terminal of the capacitor C11 is connected between the inductor L2 and the diode D2, and the other terminal of the capacitor C11 is connected between the diode D3 and the diode D4.
    • 一种用于LCD背光源的驱动电路,包括包括电容器C12,电容器C13,电感器L2,二极管D2和MOSFET的BOOST结构,其中驱动电路还包括电容器C11,电容器C14,二极管 D3和二极管D4。 二极管D3的一个端子连接到电容器C13的一个端子,另一个端子连接到二极管D4的一个端子; 二极管D4的另一个端子连接到作为电路的输出端子的电容器C14的一个端子,并且电容器C14的另一个端子接地; 电容器C11的一个端子连接在电感器L2和二极管D2之间,电容器C11的另一端连接在二极管D3和二极管D4之间。
    • 4. 发明申请
    • HIGH SPEED CHIP SCREENING METHOD USING DELAY LOCKED LOOP
    • 使用延迟锁定环路的高速芯片显示方法
    • US20110098977A1
    • 2011-04-28
    • US12607576
    • 2009-10-28
    • Junqiang SHANGLiang ZHANGYong WANGXin LIU
    • Junqiang SHANGLiang ZHANGYong WANGXin LIU
    • G06F11/30
    • G01R31/31718G01R31/31725
    • A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed.
    • 用于测量芯片的最大速度的电压控制延迟线(VCDL)包括被配置为接收参考时钟信号的第一输入,被配置为输出输出时钟信号的第一输出和被配置为接收相位误差信号的第二输入 表示参考和输出时钟信号之间的相位延迟。 寄存器将由VCDL施加的延迟码存储到参考时钟信号以延迟参考时钟信号以产生输出时钟信号。 根据相位误差信号调整延迟码,直到相位延迟等于预定值。 当相位延迟等于预定值时,第二输出耦合到从寄存器读取延迟码并将延迟代码输出到自动测试设备的接口。 输出的延迟代码对应于最大芯片速度。