专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140010013A1 MEMORY ERASING METHOD AND DRIVING CIRCUIT THEREOF 有权
标题翻译：存储器擦除方法及其驱动电路
公开(公告)号：US20140010013A1
公开(公告)日：2014-01-09
申请号：US13540803
申请日：2012-07-03
申请人： HSIAO-HUA LU , CHIH-MING KUO , YU-CHUN WANG
发明人： HSIAO-HUA LU , CHIH-MING KUO , YU-CHUN WANG
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.
摘要翻译：引入存储器擦除方法及其驱动电路，当选择要擦除单元时，该方法包括设置未被选择被擦除且位于所选块的单元的门，所选择的单元的所有单元的漏极银行，未选择的单元格的门将浮动; 为所选择的银行的所有来源提供正电压及其共享的P阱和N阱; 并向位于所选块中的单元的栅极提供负电压并选择被擦除。因此，每当门浮动时，都接收来自P阱的正耦合电压，以便禁止未选择的块的擦除，从而简化解码，从而使得容易实现具有小布局面积和扇区划分的块或块的进一步扩展在街区。

2. 发明申请

US20090158024A1 DUAL BIOS CIRCUIT 审中-公开
标题翻译：双BIOS电路
公开(公告)号：US20090158024A1
公开(公告)日：2009-06-18
申请号：US11963860
申请日：2007-12-24
申请人： JUI-TING HUNG , CHIH-MING KUO , MING-YI SHIH
发明人： JUI-TING HUNG , CHIH-MING KUO , MING-YI SHIH
IPC分类号： G06F15/177
CPC分类号： G06F11/1666 , G06F11/20
摘要： A dual BIOS circuit includes a first BIOS chip, a second BIOS chip, and a transistor. The first and the second BIOS chip include a setup program configured for setting the voltage of a GPIO pin of a Southbridge chip. The first and the second BIOS chip are connected to the Southbridge chip. The gate of the transistor is connected to the GPIO pin of the Southbridge chip. The drain of the transistor is connected to a power supply via a resistor, and connected to a detecting pin of the Southbridge chip. The source of the transistor is grounded. The power supply is connected to a signal pin of the Southbridge chip. The first or second BIOS chip is selected to operate according to the voltage level at the detecting pin of the Southbridge chip.
摘要翻译：双BIOS电路包括第一BIOS芯片，第二BIOS芯片和晶体管。第一和第二BIOS芯片包括配置用于设置南桥芯片的GPIO引脚的电压的设置程序。第一个和第二个BIOS芯片连接到南桥芯片。晶体管的栅极连接到南桥芯片的GPIO引脚。晶体管的漏极通过电阻连接到电源，并连接到南桥芯片的检测引脚。晶体管的源极接地。电源连接到南桥芯片的信号引脚。选择第一或第二BIOS芯片根据南桥芯片的检测引脚上的电压电平进行工作。

3. 发明申请

US20100037042A1 SYSTEM FOR SWITCHING BIOS SET-VALUES 审中-公开
标题翻译：用于切换BIOS设定值的系统
公开(公告)号：US20100037042A1
公开(公告)日：2010-02-11
申请号：US12238397
申请日：2008-09-25
申请人： CHIH-MING KUO
发明人： CHIH-MING KUO
IPC分类号： G06F15/177 , G06F12/02
CPC分类号： G06F9/4403
摘要： An exemplary system for switching BIOS set-values includes a south bridge chip, a memory unit, a switching unit, and a BIOS chip. The south bridge chip is connected to the memory unit and the switching unit, and connected to the BIOS chip via a bus. The memory unit is configured for storing a plurality of groups of predetermined BIOS set-values. The switching unit controls the south bridge chip to selectively read a group of BIOS set-values from the memory unit, and then to write the group of BIOS set-values into the BIOS chip.
摘要翻译：用于切换BIOS设置值的示例性系统包括南桥芯片，存储器单元，切换单元和BIOS芯片。南桥芯片连接到存储单元和交换单元，并通过总线连接到BIOS芯片。存储器单元被配置为存储多组预定的BIOS设置值。切换单元控制南桥芯片从存储器单元中选择性地读取一组BIOS设置值，然后将该组BIOS设置值写入BIOS芯片。

4. 发明申请

US20090158025A1 DUAL BIOS CIRCUIT 审中-公开
标题翻译：双BIOS电路
公开(公告)号：US20090158025A1
公开(公告)日：2009-06-18
申请号：US11963863
申请日：2007-12-24
申请人： JUI-TING HUNG , CHIH-MING KUO , MING-YI SHIH
发明人： JUI-TING HUNG , CHIH-MING KUO , MING-YI SHIH
IPC分类号： G06F15/177
CPC分类号： G06F11/1666 , G06F11/1417 , G06F11/20
摘要： A dual BIOS circuit includes a first BIOS chip, a second BIOS chip, a power supply, and a switch. The first BIOS chip is connected to a Southbridge chip of a motherboard via a bus. The second BIOS chip is connected to the Southbridge chip of a motherboard via another bus. The power supply is connected to signal pin of the Southbridge chip. The switch includes a handle. The first terminal of the switch is connected to the a detecting pin of the Southbridge chip. The second terminal of the switch is connected to the power supply. The third terminal of the switch is grounded. The first or second BIOS chip is selected to operate according to the voltage level at the detecting pin of the Southbridge chip.
摘要翻译：双BIOS电路包括第一BIOS芯片，第二BIOS芯片，电源和开关。第一个BIOS芯片通过总线连接到主板的南桥芯片。第二个BIOS芯片通过另一个总线连接到主板的南桥芯片。电源连接到南桥芯片的信号引脚。开关包括手柄。开关的第一个端子连接到南桥芯片的检测引脚。开关的第二个端子连接到电源。开关的第三端接地。选择第一或第二BIOS芯片根据南桥芯片的检测引脚上的电压电平进行工作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式